參數(shù)資料
型號: MC9328MXSCVP10R2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 100 MHz, MICROPROCESSOR, PBGA225
封裝: 13 X 13 MM, ROHS COMPLIANT, PLASTIC, MAPBGA-225
文件頁數(shù): 61/68頁
文件大小: 1335K
代理商: MC9328MXSCVP10R2
Functional Description and Application Information
MC9328MXS Technical Data, Rev. 2
64
Freescale Semiconductor
28
STCK high to STXD high impedance
17.90
29.75
15.7
26.1
ns
29
SRXD setup time before SRCK low
1.14
1.0
ns
30
SRXD hold time after SRCK low
0
0
ns
Synchronous Internal Clock Operation (Port B Alternate Function2)
31
SRXD setup before STCK falling
18.81
16.5
ns
32
SRXD hold after STCK falling
0
0
ns
Synchronous External Clock Operation (Port B Alternate Function2)
33
SRXD setup before STCK falling
1.14
1.0
ns
34
SRXD hold after STCK falling
0
0
ns
1 All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
2 There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B
alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary
function and Port B alternate function. When SSI signals are configured as inputs, the SSI module selects the input based on
FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function.
3
bl = bit length; wl = word length.
Table 29. SSI (Port B Alternate Function) Timing Parameter Table (Continued)
Ref
No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum
Maximum
Minimum
Maximum
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