參數(shù)資料
型號(hào): MC9328MXSCVP10R2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 100 MHz, MICROPROCESSOR, PBGA225
封裝: 13 X 13 MM, ROHS COMPLIANT, PLASTIC, MAPBGA-225
文件頁(yè)數(shù): 62/68頁(yè)
文件大?。?/td> 1335K
代理商: MC9328MXSCVP10R2
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-Out
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Pin-Out and Package Information
Table 30 illustrates the package pin assignments for the 225-contact MAPBGA package. For a complete listing of signals, see the
Signal Mutiplexing table in the reference manual.
Table 30. i.MXS 225 MAPBGA Pin Assignments
1
2345
678
9
10
11
12
13
14
15
A
PB13
PB15
PB19
USBD_
ROE
USBD_
SUSPND
USBD_VM
SSI_
RXFS
SSI_
TXCLK
SPI1_SPI_
RDY
SPI1_
SCLK
REV
PS
LD2
LD4
LD5
A
B
PB11
PB12
PB16
USBD_
AFE
USBD_
RCV
USBD_
VMO
SSI_
RXDAT
UART1_
TXD
SPI1_SS
LSCLK
SPL_
SPR
LD0
LD3
LD6
LD7
B
C
D31
PB8
PB14
PB18
PB10
USBD_
VPO
UART2_
RXD
SSI_
TXFS
UART1_
RTS
CONTRAST FLM/VSYNC
LD8
LD9
LD12
NVDD2
C
D
A23
A24
PB9
PB17
NVDD1
USBD_
VP
QVDD4
UART2_
TXD
NVDD3
SPI1_
MOSI
LP/HSYNC
LD1
LD11
TMR2OUT
LD13
D
E
A21
A22
D30
D29
NVDD1
QVSS
UART2_
RTS
UART1_
RXD
UART1_
CTS
SPI1_
MISO
ACD/OE
LD10
TIN
PA4
PA3
E
F
A20
A19
D28
D27
NVDD1
UART2_
CTS
SSI_
RXCLK
SSI_
TXDAT
CLS
QVDD3
LD14
LD15
PA6
PA8
F
G
A17
A18
D26
D25
NVDD1
NVSS
NVDD4
NVSS
QVSS
PWMO
PA7
PA11
PA13
PA9
G
H
A15
A16
D23
D24
D22
NVSS
NVDD2
PA5
PA12
PA14
I2C_SDA
TMS
H
J
A14
A12
D21
D20
NVDD1
NVSS
QVDD1
NVSS
PA10
I2C_SCL
TCK
TDO
BOOT1
BOOT0
J
K
A13
A11
CS2
D19
NVDD1
NVSS
QVSS
NVDD1
NVSS
D1
BOOT2
TDI
BIG_
ENDIAN
RESET_
OUT
XTAL32K
K
L
A10
A9
D17
D18
NVDD1
CS5
D2
ECB
NVSS
POR
QVSS
XTAL16M
EXTAL32K
L
M
D16
D15
D13
D10
EB3
NVDD1
CS4
CS1
BCLK1
1 Burst Clock
RW
NVSS
BOOT3
QVDD2
RESET_IN
EXTAL16M
M
N
A8
A7
D12
EB0
D9
D8
CS3
CS0
PA17
D0
DQM2
DQM0
SDCKE0
TRISTATE
TRST
N
P
D14
A5A4
A3A2A1
D6
D5
MA10
MA11
DQM1
RAS
SDCKE1
CLKO
RESET_SF2
2 This signal is not used on the i.MXS and should be floated in an actual application.
P
R
A6
D11
EB1
EB2
OE
D7
A0
SDCLK
D4
LBA
D3
DQM3
CAS
SDWE
AVDD1
R
1
2345
678
9
10
11
12
13
14
15
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