參數(shù)資料
型號: MCIMX27LMOP4AR2
廠商: Freescale Semiconductor
文件頁數(shù): 138/152頁
文件大?。?/td> 0K
描述: IC MPU I.MX27 IN 19X19 473MAPBGA
標(biāo)準(zhǔn)包裝: 750
系列: i.MX27
核心處理器: ARM9
芯體尺寸: 32-位
速度: 400MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,LCD,POR,PWM,WDT
程序存儲器類型: ROMless
RAM 容量: 45K x 8
電壓 - 電源 (Vcc/Vdd): 1.38 V ~ 1.52 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 473-LFBGA
包裝: 帶卷 (TR)
i.MX27 and i.MX27L Data Sheet, Rev. 1.8
86
Freescale Semiconductor
Electrical Characteristics
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0)
and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or
the frame sync STFS/SRFS shown in the tables and in the figures.
All timings are on AUDMUX pads when SSI is being used for data transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx
Data (for example, during AC97 mode of operation).
4.3.11.2
SSI Receiver Timing with Internal Clock
Figure 47 and Figure 48 show the SSI receiver timing with internal clock, and Table 47 lists the timing
parameters.
Figure 47. SSI Receiver with Internal Clock Timing Diagram
Synchronous Internal Clock Operation
SS42
SRXD setup before (Tx) CK falling
10.0
ns
SS43
SRXD hold after (Tx) CK falling
0
ns
SS52
Loading
25
pF
Table 46. SSI Transmitter with Internal Clock Timing Parameters (continued)
ID
Parameter
Min
Max
Unit
SS50
SS48
AD1_TXC
AD1_TXFS (bl)
AD1_TXFS (wl)
AD1_RXD
AD1_RXC
SS1
SS4
SS2
SS51
SS20
SS21
SS49
SS7
SS9
SS11
SS13
SS47
(Output)
(Input)
(Output)
SS3
SS5
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