參數(shù)資料
型號: MCIMX27VOP4
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA404
封裝: 17 X 17 MM, 0.65 MM PITCH, LEAD FEE, MAPBGA-404
文件頁數(shù): 94/118頁
文件大?。?/td> 1159K
代理商: MCIMX27VOP4
Signal Descriptions
i.MX27 Data Sheet, Advance Information, Rev. 0.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
77
Figure 40. Mobile DDR SDRAM Write Cycle Timing Diagram
NOTE
SDRAM CLK and DQS related parameters are being measured from the
50% point—that is, high is defined as 50% of signal value and low is
defined as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 40 indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
Table 40. Mobile DDR SDRAM Write Cycle Timing Parameters1
1 Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.
ID
Parameter
Symbol
Min
Max
Unit
SD17
DQ and DQM setup time to DQS
tDS
0.95
ns
SD18
DQ and DQM hold time to DQS
tDH
0.95
ns
SD19
Write cycle DQS falling edge to SDCLK output delay time.
tDSS
1.8
ns
SD20
Write cycle DQS falling edge to SDCLK output hold time.
tDSH
1.8
ns
SDCLK
DQS (output)
DQ (output)
DQM (output)
Data
DM
SD17
SD18
SD19
SD20
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