參數(shù)資料
型號: MCIMX31LDVKN5D
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 532 MHz, MICROPROCESSOR, PBGA457
封裝: 14 X 14 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-457
文件頁數(shù): 48/118頁
文件大小: 1083K
代理商: MCIMX31LDVKN5D
Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
35
4.3.8
DPLL Electrical Specifications
The three PLL’s of the MCIMX31 (MCU, USB, and Serial PLL) are all based on same DPLL design. The
characteristics provided herein apply to all of them, except where noted explicitly. The PLL characteristics
are provided based on measurements done for both sources—external clock source (CKIH), and FPM
(Frequency Pre-Multiplier) source.
4.3.8.1
Electrical Specifications
Table 30 lists the DPLL specification.
Table 29. CSPI Interface Timing Parameters
ID
Parameter
Symbol
Min
Max
Units
CS1
SCLK Cycle Time
tclk
60
ns
CS2
SCLK High or Low Time
tSW
30
ns
CS3
SCLK Rise or Fall
tRISE/FALL
—7.6
ns
CS4
SSx pulse width
tCSLH
25
ns
CS5
SSx Lead Time (CS setup time)
tSCS
25
ns
CS6
SSx Lag Time (CS hold time)
tHCS
25
ns
CS7
Data Out Setup Time
tSmosi
5—
ns
CS8
Data Out Hold Time
tHmosi
5—
ns
CS9
Data In Setup Time
tSmiso
6—
ns
CS10
Data In Hold Time
tHmiso
5—
ns
CS11
SPI_RDY Setup Time1
1 SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
tSRDY
——
ns
Table 30. DPLL Specifications
Parameter
Min
Typ
Max
Unit
Comments
CKIH frequency
15
261
752
MHz
CKIL frequency
(Frequency Pre-multiplier (FPM) enable mode)
32; 32.768, 38.4
kHz FPM lock time
≈ 480 s.
Predivision factor (PD bits)
1
16
PLL reference frequency range after Predivider
15
35
MHz 15
≤ CKIH frequency/PD ≤ 35 MHz
15
≤ FPM output/PD ≤ 35 MHz
PLL output frequency range:
MPLL and SPLL
UPLL
52
190
532
240
MHz
Maximum allowed reference clock phase noise.
± 100 ps
Frequency lock time
(FOL mode or non-integer MF)
398
Cycles of divided reference clock.
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