參數(shù)資料
型號(hào): MCIMX31LDVKN5D
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 532 MHz, MICROPROCESSOR, PBGA457
封裝: 14 X 14 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-457
文件頁數(shù): 66/118頁
文件大?。?/td> 1083K
代理商: MCIMX31LDVKN5D
Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
51
Figure 37. Mobile DDR SDRAM Write Cycle Timing Diagram
NOTE
SDRAM CLK and DQS related parameters are being measured from the
50% point—that is, high is defined as 50% of signal value and low is
defined as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 37 indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
Table 37. Mobile DDR SDRAM Write Cycle Timing Parameters1
1 Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.
ID
Parameter
Symbol
Min
Max
Unit
SD17
DQ and DQM setup time to DQS
tDS
0.95
ns
SD18
DQ and DQM hold time to DQS
tDH
0.95
ns
SD19
Write cycle DQS falling edge to SDCLK output delay time.
tDSS
1.8
ns
SD20
Write cycle DQS falling edge to SDCLK output hold time.
tDSH
1.8
ns
SDCLK
DQS (output)
DQ (output)
DQM (output)
Data
DM
SD17
SD18
SD19
SD20
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