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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MCIMX356AVM4B |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 111/147闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC MPU I.MX35 400MAPBGA |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | i.MX35 |
| 鏍稿績铏曠悊鍣細 | ARM11 |
| 鑺珨灏哄锛� | 32-浣� |
| 閫熷害锛� | 400MHz |
| 閫ｉ€氭€э細 | 1 绶�锛孋AN锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孧MC锛孲PI锛孲SI锛孶ART/USART锛孶SB OTG |
| 澶栧湇瑷�(sh猫)鍌欙細 | DMA锛孖²S锛孡CD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 96 |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | ROMless |
| RAM 瀹归噺锛� | 128K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.22 V ~ 1.47 V |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 400-LFBGA |
| 鍖呰锛� | 鎵樼洡 |
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i.MX35 Applications Processors for Automotive Products, Rev. 10
Freescale Semiconductor
66
4.9.11
I2C AC Electrical Specifications
This section describes the electrical characteristics of the I2C module.
4.9.11.1
I2C Module Timing
Figure 43. I2C Bus Timing Diagram
Table 52. I2C Module Timing Parameters
ID
Parameter
Standard Mode
Fast Mode
Unit
Min.
Max.
Min.
Max.
IC1
I2CLK cycle time
10
鈥�
2.5
鈥�
渭s
IC2
Hold time (repeated) START condition
4.0
鈥�
0.6
鈥�
渭s
IC3
Set-up time for STOP condition
4.0
鈥�
0.6
鈥�
渭s
IC4
Data hold time
01
1 A device must internally provide a hold time of at least 300 ns for the I2DAT signal in order to bridge the undefined region of
the falling edge of I2CLK.
3.452
2 The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal.
渭s
IC5
HIGH Period of I2CLK Clock
4.0
鈥�
0.6
鈥�
渭s
IC6
LOW Period of the I2CLK Clock
4.7
鈥�
1.3
鈥�
渭s
IC7
Set-up time for a repeated START condition
4.7
鈥�
0.6
鈥�
渭s
IC8
Data set-up time
250
鈥�
1003
3 A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement of set-up time (ID IC7) of
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line
max_rise_time (ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus
specification) before the I2CLK line is released.
鈥攏s
IC9
Bus free time between a STOP and START condition
4.7
鈥�
1.3
鈥�
渭s
IC10
Rise time of both I2DAT and I2CLK signals
鈥�
1000
鈥�
300
ns
IC11
Fall time of both I2DAT and I2CLK signals
鈥�
300
鈥�
300
ns
IC12
Capacitive load for each bus line (Cb)鈥�
400
鈥�
400
pF
IC10
IC11
IC9
IC2
IC8
IC4
IC7
IC3
IC6
IC10
IC5
IC11
START
STOP
START
I2DAT
I2CLK
IC1
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| MCIMX356AVM4BR2 | 鍔熻兘鎻忚堪:铏曠悊鍣� - 灏堥杸鎳�(y墨ng)鐢� i.MX35 Auto Apps Processor RoHS:鍚� 鍒堕€犲晢:Freescale Semiconductor 椤炲瀷:Multimedia Applications 鏍稿績:ARM Cortex A9 铏曠悊鍣ㄧ郴鍒�:i.MX6 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:1 GHz 鎸囦护/鏁�(sh霉)鎿�(j霉)绶╁瓨: 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鏁�(sh霉)鎿�(j霉) ROM 澶у皬: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�:+ 95 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MAPBGA-432 |
| MCIMX356AVM5B | 鍔熻兘鎻忚堪:铏曠悊鍣� - 灏堥杸鎳�(y墨ng)鐢� RINGO MX35 TO2 RoHS:鍚� 鍒堕€犲晢:Freescale Semiconductor 椤炲瀷:Multimedia Applications 鏍稿績:ARM Cortex A9 铏曠悊鍣ㄧ郴鍒�:i.MX6 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:1 GHz 鎸囦护/鏁�(sh霉)鎿�(j霉)绶╁瓨: 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鏁�(sh霉)鎿�(j霉) ROM 澶у皬: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�:+ 95 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MAPBGA-432 |
| MCIMX356AVM5BR2 | 鍔熻兘鎻忚堪:铏曠悊鍣� - 灏堥杸鎳�(y墨ng)鐢� RINGO MX35 TO2 RoHS:鍚� 鍒堕€犲晢:Freescale Semiconductor 椤炲瀷:Multimedia Applications 鏍稿績:ARM Cortex A9 铏曠悊鍣ㄧ郴鍒�:i.MX6 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:1 GHz 鎸囦护/鏁�(sh霉)鎿�(j霉)绶╁瓨: 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鏁�(sh霉)鎿�(j霉) ROM 澶у皬: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�:+ 95 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MAPBGA-432 |
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