參數(shù)資料
型號(hào): MCP25050-E/SL
廠商: Microchip Technology
文件頁(yè)數(shù): 41/66頁(yè)
文件大?。?/td> 0K
描述: IC I/O EXPANDER CAN 8B 14SOIC
標(biāo)準(zhǔn)包裝: 57
接口: CAN
輸入/輸出數(shù): 8
中斷輸出: 無(wú)
頻率 - 時(shí)鐘: 25MHz
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOIC
包裝: 管件
包括: ADC,存儲(chǔ)器,PWM
其它名稱: MCP25050E/SL
MCP2502X/5X
DS21664D-page 46
2007 Microchip Technology Inc.
REGISTER 7-9:
A/D OM RESULT REGISTER (AN10L)
TABLE 7-2:
REGISTERS ASSOCIATED WITH THE A/D MODULE
R-x
U-x
R-x
U-x
AN1R.1
AN1R.0
AN0R.1
AN0R.0
bit 7
bit 0
bit 7-6
AN1R.1:AN1R.0: A/D Channel 1, bits 1:0 results
bit 5-4
Unimplemented: Reads as ‘0’
bit 3-2
AN0R.1:AN0R.0: A/D Channel 0, bits 1:0 results
bit 1-0
Unimplemented: Reads as ‘0’
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
Addr
Name
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Value on
POR
Value on
RST
1Eh
GPPIN
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
0000 0000
34h
GPDDR *
DDR6
DDR5
DDR4
DDR3
DDR2
DDR1
DDR0
-111 1111
00h
IOINTEN
GP7TXC
GP6TXC
GP5TXC
GP4TXC
GP3TXC
GP2TXC
GP1TXC
GP0TXC
0000 0000
01h
IOINTPO
GP7POL
GP6POL
GP5POL
GP4POL
GP3POL
GP2POL
GP1POL
GP0POL
0000 0000
0Eh
ADCON0
ADON
T0PS2
T0PS1
T0PS0
GO/DONE
CHS1
CHS0
0000 0-00
0Fh
ADCON1
ADCS1
ADCS0
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
0000 0000
2Ch
ADCMP3
AN3CM
AN3CMP.
AN3CMP.5
AN3CMP.4
AN3CMP.
AN3CMP2 xxxx xxxx
uuuu uuuu
2Dh
ADCMP3
AN3CM
AN3CMP.
—Reserved
ADPOL
xx-- ----
uu-- ----
2Eh
ADCMP2
AN2CM
AN2CMP.
AN2CMP.5
AN2CMP.4
AN2CMP.
AN2CMP2 xxxx xxxx
uuuu uuuu
2Fh
ADCMP2
AN2CM
AN2CMP.
—Reserved
ADPOL
xx-- ----
uu-- ----
30h
ADCMP1
AN1CM
AN1CMP.
AN1CMP.5
AN1CMP.4
AN1CMP.
AN1CMP2 xxxx xxxx
uuuu uuuu
31h
ADCMP1
AN1CM
AN1CMP.
—Reserved
ADPOL
xx-- ----
uu-- ----
32h
ADCMP0
AN0CM
AN0CMP.
AN0CMP.5
AN0CMP.4
AN0CMP.
AN0CMP2 xxxx xxxx
uuuu uuuu
33h
ADCMP0
AN0CM
AN0CMP.
Reserved
xx-- ----
uu-- ----
10h
STCON
STEM
STMS
STBF1
STBF0
STM3
STM2
STM1
STM0
0xxx xxxx
0uuu uuuu
*
The GPDDR register controls the direction of the GPIO pins, even when they are being used as analog inputs. The user must ensure
that the bits in the GPDDR register are maintained set (input) when using them as analog inputs
.
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