參數(shù)資料
型號(hào)： MCP25050-E/SL
廠商： Microchip Technology
文件頁數(shù)： 56/66頁
文件大?。?/td> 0K
描述： IC I/O EXPANDER CAN 8B 14SOIC
標(biāo)準(zhǔn)包裝： 57
接口： CAN
輸入/輸出數(shù)： 8
中斷輸出： 無
頻率 - 時(shí)鐘： 25MHz
電源電壓： 4.5 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 14-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 14-SOIC
包裝： 管件
包括： ADC，存儲(chǔ)器，PWM
其它名稱： MCP25050E/SL
MCP2502X/5X
DS21664D-page 6
2007 Microchip Technology Inc.
2.1
CAN Protocol Finite State Machine
The heart of the engine is the Finite State Machine
(FSM).
This
state
machine
sequences
through
messages on a bit-by-bit basis, changing states as the
fields of the various frame types are transmitted or
received. The FSM is a sequencer controlling the
sequential data stream between the TX/RX Shift
register, the CRC register and the bus line. The FSM
also controls the Error Management Logic (EML) and
the parallel data stream between the TX/RX Shift
registers and the buffers. The FSM insures that the pro-
cesses of reception, arbitration, transmission and error
signaling are performed according to the CAN protocol.
The automatic retransmission of messages on the bus
line is also handled.
2.2
Cyclic Redundancy Check (CRC)
The Cyclic Redundancy Check register generates the
Cyclic Redundancy Check (CRC) code that is
transmitted after either the Control field (for messages
with 0 data bytes) or the Data field and is used to check
the CRC field of incoming messages.
2.3
Error Management Logic
The error management logic is responsible for the fault
confinement of the CAN device. Its two counters (the
Receive Error Counter (REC) and the Transmit Error
Counter (TEC)) are incremented and decremented by
commands from the Bit Stream processor. According to
the values of the error counters, the MCP2502X/5X is
set into the states error-active, error-passive or bus-off.
Error-active: Both error counters are below the error-
passive limit of 128.
Error-passive: At least one of the error counters (TEC
or REC) equals or exceeds 128.
Bus-off: The transmit error counter (TEC) equals or
exceeds the bus-off limit of 256. The device remains in
this state until the bus-off recovery sequence is
received. The bus-off recovery sequence consists of
128 occurrences of 11 consecutive recessive bits.
FIGURE 2-2:
ERROR MODES STATE DIAGRAM
Note:
The MCP2502X/5X, after going bus-off,
will
recover
back
to
error-active
automatically if the bus remains idle for
128 x 11 bits. OPTREG2.ERRE must be
set to force the MCP2502X/5X to enter
Listen-only mode instead of Normal mode
during bus recovery. The current error
mode
(except
for
bus-off)
of
the
MCP2502X/5X can be determined by
reading the EFLG register via the Read
CAN error message.
Bus-Off
Error-Active
Error-Passive
REC < 127 or
TEC < 127
REC > 127 or
TEC > 127
TEC > 255
RESET
128 occurrences of
11 consecutive
“recessive” bits
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