Output Buffer/VOUT
參數(shù)資料
型號： MCP4716A0T-E/MAY
廠商： Microchip Technology
文件頁數(shù)： 31/86頁
文件大?。?/td> 0K
描述： IC DAC 10BIT NV EEP I2C 6DFN
標準包裝： 1
設(shè)置時間： 6µs
位數(shù)： 10
數(shù)據(jù)接口： EEPROM，I²C，串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 1.10W
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 6-VDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 6-DFN（2x2）
包裝： 標準包裝
輸出數(shù)目和類型： 1 電壓，單極
采樣率（每秒）： *
其它名稱： MCP4716A0T-E/MAYDKR
2011-2012 Microchip Technology Inc.
DS22272C-page 37
MCP4706/4716/4726
4.4
Output Buffer/VOUT Operation
The DAC output is buffered with a low power and
precision output amplifier (op amp). Figure 4-4 shows
a block diagram.
This amplifier provides a rail-to-rail output with low
offset voltage and low noise. The user can select the
output gain of the output amplifier. Gain options are:
a)
Gain of 1, with either VDD or VREF pin used as
reference voltage
b)
Gain of 2, only when VREF pin is used as
reference voltage. The VREF pin voltage should
be limited to VDD/2.
The amplifier’s output can drive the resistive and high
capacitive loads without oscillation. The amplifier
provides a maximum load current which is enough for
most programmable voltage reference applications.
the specifications of the output amplifier.
In any of the three Power-Down modes, the op amp is
powered down and its output becomes a high-
impedance to the VOUT pin.
FIGURE 4-4:
Output Buffer Block
Diagram.
4.4.1
PROGRAMMABLE GAIN
The amplifier’s gain is controlled by the Gain (G)
Configuration bit (See Table 4-4) and the VRL reference
selection. When the VRL reference selection is the
device’s VDD voltage, the G bit is ignored and a gain of
1 is used. The volatile G bit value can be modified by:
POR event
BOR event
I2C Write commands
I2C General Call Reset command
4.4.2
OUTPUT VOLTAGE
The volatile DAC register’s value controls the analog
VOUT voltage, along with the device’s five Configuration
bits. The volatile DAC register’s value is unsigned
binary.
The formula for the output voltage is given in
Equation 4-1. Table 4-1 shows examples of volatile
DAC register values and the corresponding theoretical
VOUT voltage for the MCP47X6 devices.
EQUATION 4-1:
CALCULATING OUTPUT
VOLTAGE (VOUT)
The DAC register value will be latched on the falling
edge
of
the
Acknowledge
pulse
of
the
Write
command’s last byte. Then the VOUT voltage will start
driving to the new value.
The following events update the analog voltage output
(VOUT):
Power-on Reset or General Call Reset command:
Output is updated with EEPROM data.
Falling edge of the Acknowledge pulse of the last
Write command byte.
4.4.2.1
Resolution/Step Voltage
The Step voltage is dependent on the device resolution
and the output voltage range. One LSb is defined as
the ideal voltage difference between two successive
codes. The step voltage can easily be calculated by
using Equation 4-1 where the DAC register value is
equal to 1.
Note:
The load resistance must stay higher than
5k
Ω for the stable and expected analog
output to meet electrical specifications.
VOUT
Op
Amp
Gain (1x or 2x)
(G = 0 or 1)
VW
Note:
When Gain = 2 (VRL = VREF),
if VREF > VDD/2, the VOUT voltage will be
limited to VDD. So if VREF = VDD, then the
VOUT voltage will not change for volatile
DAC
register
values
mid-scale
and
greater, since the op amp is at its full scale
output.
VOUT =
* Gain
VRL * DAC Register Value
# Resistors in Resistor Ladder
# Resistors in Resistor Ladder = 4096 (MCP4726)
1024 (MCP4716)
256 (MCP4706)
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