V
參數(shù)資料
型號(hào)： MCP4716A0T-E/MAY
廠商： Microchip Technology
文件頁(yè)數(shù)： 45/86頁(yè)
文件大?。?/td> 0K
描述： IC DAC 10BIT NV EEP I2C 6DFN
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 6µs
位數(shù)： 10
數(shù)據(jù)接口： EEPROM，I²C，串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 1.10W
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 6-VDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 6-DFN（2x2）
包裝： 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型： 1 電壓，單極
采樣率（每秒）： *
其它名稱： MCP4716A0T-E/MAYDKR
2011-2012 Microchip Technology Inc.
DS22272C-page 5
MCP4706/4716/4726
Output Amplifier
Minimum Output
Voltage
VOUT(MIN)
—
0.01
—
V
Output Amplifier’s minimum drive
Maximum Output
Voltage
VOUT(MAX)
—VDD –
0.04
—
V
Output Amplifier’s maximum drive
Phase Margin
PM
—
66
—
Degree
(°)
CL = 400 pF, RL = ∞
Slew Rate
SR
—
0.55
—
V/s
Short Circuit Current
ISC
715
24
mA
Settling Time
tSETTLING
—6—
s
Power-Down Output
Disable Time Delay
TPDD
—
1
—
s
PD1:PD0 = 00 -> 11, ‘10’, or ‘01’
started from falling edge SCL at end of
ACK bit.
VOUT = VOUT - 10 mV. VOUT not
connected.
Power-Down Output
Enable Time Delay
TPDE
—
10.5
—
s
PD1:PD0 = 11, ‘10’, or ‘01’ -> “00”
started from falling edge SCL at end of
ACK bit.
Volatile DAC Register = FFh,
VOUT =10mV. VOUT not connected.
External Reference (VREF) (Note 1)
Input Range
VREF
0.04
—
VDD -
0.04
V
Buffered mode
0—
VDD
V
Unbuffered mode
Input Impedance
RVREF
—
210
—
k
Ω
Unbuffered mode
Input Capacitance
C_REF
—
29
—
pF
Unbuffered mode
-3 dB Bandwidth
—
86.5
—
kHz
VREF = 2.048V ± 0.1V,
VREF1:VREF0 = 10, G = 0
—67.7—
kHz
VREF = 2.048V ± 0.1V,
VREF1:VREF0 = 10, G = 1
Total Harmonic
Distortion
THD
—
-73
—
dB
VREF = 2.048V ± 0.1V,
VREF1:VREF0 = 10, G = 0,
Frequency = 1 kHz
Dynamic Performance (Note 1)
Major Code Transition
Glitch
—
45
—
nV-s
1 LSb change around major carry
(800h to 7FFh)
Digital Feedthrough
—
<10
—
nV-s
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V, RL = 5 kΩ from VOUT to GND, CL = 100 pF,
TA = -40°C to +125°C. Typical values at +25°C.
Parameters
Symbol
Min
Typical
Max
Units
Conditions
Note
1:
This parameter is ensured by design and is not 100% tested.
2:
This Gain error does not include Offset error. See Section 1.0 “Electrical Characteristics” for more details in plots.
3:
Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit device).
4:
The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of VDD
over time.
5:
This parameter is ensured by characterization, and not 100% tested.
6:
The PD1:PD0 = 10, and ‘11’ configurations should have the same current.
7:
VDD = VREF = 5.5V.
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