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參數(shù)資料
| 型號： | MCP4725A0T-E/CH |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 13/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT W/I2C SOT23A-6 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | EEPROM，I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-6 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 673 (CN2011-ZH PDF) |
| 配用： | MCP4725DM-PTPLS-ND - BOARD DAUGHTER PICTAIL MCP4725 |
| 其它名稱： | MCP4725A0T-E/CHDKR MCP4725AOT-E/CHDKR MCP4725AOT-E/CHDKR-ND |
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MCP4725
DS22039D-page 20
2009 Microchip Technology Inc.
5.4.2
VDD RAMP RATE AND EEPROM
The MCP4725 uploads the EEPROM data to the DAC
register during power-up sequence. However, if the
VDD ramp rate is too slow ( <1 V/ms), the device may
not be able to load the EEPROM data to the DAC
register. Therefore, the DAC output that is correspond-
ing to the current EEPROM data may not available to
the output pin. It is highly recommended to send a Gen-
eral Call Reset Command (see Section 7.3.1 “Gen-
eral call reset”) after power-up. This command will
reset the device at a stable VDD and make the DAC out-
put available immediately using the EEPROM data.
5.5
Normal and Power-Down Modes
The device has two modes of operation: Normal mode
and power-down mode. The mode is selected by
programming the power-down bits (PD1 and PD0) in
the Configuration register. The user can also program
the two power-down bits in non-volatile EEPROM
memory.
When the normal mode is selected, the device
operates a normal digital-to-analog conversion. If the
power-down mode is selected, the device enters a
power saving condition by shutting down most of the
internal circuits. During the power-down mode, all
internal circuits except the I2C interface are disabled
and there is no data conversion event, and no VOUT is
available. The device also switches the output stage
from the output of the amplifier to a known resistive
load. The value of the resistive load is determined by
the state of the power-down bits (PD1 and PD0).
Table 5-2 shows the outcome of the power-down bit
and the resistive load.
During the power-down mode, the device draws about
60 nA (typical). Although most of internal circuits are
shutdown, the serial interface remains active in order
to receive the I2C command.
The device exits the power-down mode immediately
when (a) it receives a new write command for normal
mode or (b) it receives an I2C General Call Wake-Up
Command.
When the DAC operation mode is changed from
power-down to normal mode, the output settling time
takes less than 10 s, but greater than the standard
Active mode settling time (6 s, typical).
TABLE 5-2:
POWER-DOWN BITS
FIGURE 5-1:
Output Stage for Power-
Down Mode.
PD1
PD0
Function
00
Normal Mode
01
1k resistor to ground (1)
10
100 k resistor to ground (1)
11
500 k resistor to ground (1)
Note 1: In the power-down mode: VOUT is off and
most of internal circuits are disabled.
1k
100 k 500 k
Power-Down
Control Circuit
Resistive
Load
VOUT
OP
Amp
Resistive String DAC
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