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參數(shù)資料
| 型號(hào)： | MCP4726A0T-E/MAY |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 29/86頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT NV EEP I2C 6DFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | EEPROM，I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1.10W |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-VDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 6-DFN（2x2） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
| 其它名稱： | MCP4726A0T-E/MAYDKR |
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2011-2012 Microchip Technology Inc.
DS22272C-page 35
MCP4706/4716/4726
4.0
GENERAL DESCRIPTION
The MCP4706, MCP4716, and MCP4726 devices are
single channel voltage output 8-bit, 10-bit, and 12-bit
DAC devices with nonvolatile memory (EEPROM) and
an I2C serial interface. This family will be referred to as
MCP47X6.
The devices use a resistor ladder architecture. The
resistor ladder DAC is driven from a software
selectable voltage reference source. The source can
be either the device’s internal VDD or the external VREF
pin voltage.
The DAC output is buffered with a low power and
precision output amplifier (op amp). This output
amplifier provides a rail-to-rail output with low offset
voltage and low noise. The gain of the output buffer is
software configurable.
This device also has user programmable nonvolatile
memory (EEPROM), which allows the user to save the
desired POR/BOR value of the DAC register and
device Configuration bits.
The devices use a two-wire I2C serial communication
interface and operate with a single supply voltage from
2.7V to 5.5V.
4.1
Power-On Reset/Brown-Out Reset
(POR/BOR)
The internal Power-on Reset (POR)/Brown-out Reset
(BOR) circuit monitors the power supply voltage (VDD)
during operation. This circuit ensures correct device
start-up at system power-up and power-down events.
VRAM is the RAM retention voltage and is always lower
than the POR trip point voltage.
POR occurs as the voltage is rising (typically from 0V),
while BOR occurs as the voltage is falling (typically
from VDD(MIN) or higher).
When the rising VDD voltage crosses the VPOR trip
point, the following occurs:
Nonvolatile DAC register value latched into
volatile DAC register
Nonvolatile Configuration bit values latched into
volatile Configuration bits
POR Status bit is set (“1”)
The Reset delay timer starts; when timer times
out (tPORD), the I
2C interface is operational.
The analog output (VOUT) state will be determined by
the state of the volatile Configuration bits and the DAC
register. This is called a POR Reset (event).
When the falling VDD voltage crosses the VPOR trip
point, the following occurs:
Device is forced into a power-down state
(PD1:PD0 = 11). Analog circuitry is turned off.
Volatile DAC register is forced to 000h
Volatile Configuration bits VREF1, VREF0 and G
are forced to ‘0’
Figure 4-1 illustrates the conditions for power-up and
power-down events under typical conditions.
FIGURE 4-1:
Power-on Reset Operation.
VPOR
TPORD
VDD(MIN)
Normal Operation
BOR Reset,
volatile DAC Register = 000h
volatile VREF1:VREF0 = 00
Device in
Below
VRAM
Device in
POR state
unknown
state
minimum
operating
voltage
Device in
unknown
state
Device
in power
down
state
(60 s max.)
volatile G = 0
volatile PD1:PD0 = 11
VBOR
Volatile memory
retains data value
Volatile memory
becomes corrupted
POR starts Reset Delay Timer.
When timer times out, I2C interface
can operate (if VDD >= VDD(MIN))
EEPROM data latched into volatile
Configuration bits and DAC register.
POR Status bit is set (“1”)
POR Reset forced active
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