參數(shù)資料
型號： MCP4726A0T-E/MAY
廠商： Microchip Technology
文件頁數(shù)： 36/86頁
文件大小： 0K
描述： IC DAC 12BIT NV EEP I2C 6DFN
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 6µs
位數(shù)： 12
數(shù)據(jù)接口： EEPROM，I²C，串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 1.10W
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 6-VDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 6-DFN（2x2）
包裝： 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型： 1 電壓，單極
采樣率（每秒）： *
其它名稱： MCP4726A0T-E/MAYDKR
2011-2012 Microchip Technology Inc.
DS22272C-page 41
MCP4706/4716/4726
4.6
Device Resets
Device Resets can be grouped into two types: Resets
due to change in voltage (POR/BOR Reset), and
Resets caused by the system master (such as a
microcontroller).
After a device Reset, and when VDD ≥ VDD(MIN), the
device memory may be written or read.
4.6.1
POR/BOR RESET OPERATION
The POR and BOR trip points are at the same voltage,
and are determined if the VDD voltage is rising or falling
(see Figure 4-1). What occurs is different, depending if
the Reset is a POR or BOR Reset.
POR Reset (VDD Rising)
On a POR Reset, the nonvolatile memory values (DAC
register and Configuration bits) are latched into the
volatile memory. This configures the analog output
(VOUT) circuitry. A Reset delay timer also starts. During
this delay time, the I2C interface will not accept
commands.
BOR Reset (VDD Falling)
On a BOR Reset, the device is forced into a power-
down state. The volatile PD1:PD0 bits are forced to ‘11’
and all other volatile memory forced to ‘0’. The I2C
interface will not accept commands.
4.6.2
RESET COMMANDS
When the MCP47X6 is in the valid operating voltage,
the I2C General Call Reset command will force a
Reset event. This is similar to the POR Reset, except
that the Reset delay timer is not started.
In the case where the I2C interface bus does not seem
to be responsive, the technique shown in Section 8.9
used to force the I2C interface to be reset.
4.7
DAC Registers, Configuration
Bits, and Status Bits
The MCP47X6 devices have both volatile and
nonvolatile (EEPROM) memory. Figure 4-8 shows the
volatile and nonvolatile memory and their interaction
due to a POR event.
There are five Configuration bits in both the volatile and
nonvolatile memory, the DAC registers in both the
volatile and nonvolatile memory, and two volatile Status
bits. The DAC registers (volatile and nonvolatile) will be
either 12-bits (MCP4726), 10-bits (MCP4716), or 8-bits
(MCP4706) wide.
When the device is first powered up, it automatically
uploads the EEPROM memory values to the volatile
memory. The volatile memory determines the analog
output (VOUT) pin voltage. After the device is powered
up, the user can update the device memory.
The I2C interface is how this memory is read and
more details on the reading and writing the device’s
memory.
When the nonvolatile memory is written (using the I2C
Write All Memory command), the volatile memory is
written with the same values. The device starts writing
the EEPROM cell at the Acknowledge pulse of the
EEPROM Write command.
Table 4-3 shows the operation of the device Status bits,
Table 4-4 shows the operation of the device Configura-
tion bits, and Table 4-5 shows the factory default value
of a POR/BOR event for the device Configuration bits.
There are two Status bits. These are only in volatile
memory and give indication on the status of the device.
The POR bit indicates if the device VDD is above or
below the POR trip point. During normal operation, this
bit should be ‘1’. The RDY/BSY bit indicates if an
EEPROM write cycle is in progress. While the
RDY/BSY bit is low (during the EEPROM writing), all
commands are ignored, except for the Read command.
FIGURE 4-8:
DAC Memory and POR Interaction.
VREF1
DAC Register Value (1)
N.V. Memory
Config Bits
Vol. Memory
POR Event
VREF0
PD1
PD0
G
VREF1 VREF0
PD1
PD0
G
RDY/BSY
POR
Status Bits (2)
DMAX
D1
D0
DMAX
D1
D0
Note 1: The DMAX value depends on the device. For the MCP4706: DMAX = D7, MCP4716: DMAX = D9,
and the MCP4726: DMAX = D11.
2: Status bits are read-only.
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