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參數(shù)資料
型號： MCP639T-E/ML
廠商： Microchip Technology
文件頁數(shù)： 17/62頁
文件大小： 0K
描述： IC OP AMP QUAD 24MHZ 16-QFN
標準包裝： 3,300
放大器類型： 通用
電路數(shù)： 4
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 10 V/µs
增益帶寬積： 24MHz
電流 - 輸入偏壓： 4pA
電壓 - 輸入偏移： 1800µV
電流 - 電源： 2.5mA
電流 - 輸出 / 通道： 70mA
電壓 - 電源，單路/雙路(±)： 2.5 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-VQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 16-QFN（4x4）
包裝： 帶卷 (TR)
MCP631/2/3/4/5/9
DS22197B-page 24
2009-2011 Microchip Technology Inc.
CN and RN form a low-pass filter that affects the signal
at VP. This filter has a single real pole at 1/(2RNCN).
The largest value of RF that should be used depends
on noise gain (see GN in Section 4.3.1 “Capacitive
Loads”), CG and the open-loop gain’s phase shift.
Figure 4-9 shows the maximum recommended RF for
several CG values. Some applications may modify
these values to reduce either output loading or gain
peaking (step response overshoot).
FIGURE 4-9:
Maximum Recommended
RF vs. Gain.
Figure 2-34 and Figure 2-35 show the small signal and
large signal step responses at G = +1 V/V. The unity
gain buffer usually has RF =0 and RG open.
Figure 2-36 and Figure 2-37 show the small signal and
large signal step responses at G = -1 V/V. Since the
noise gain is 2 V/V and CG 10 pF, the resistors were
chosen to be RF =RG =1 k and RN = 500.
It is also possible to add a capacitor (CF) in parallel with
RF to compensate for the de-stabilizing effect of CG.
This makes it possible to use larger values of RF. The
conditions for stability are summarized in Equation 4-6.
EQUATION 4-6:
4.4
MCP631, MCP633, MCP635, and
MCP639 Chip Select
The MCP633 is a single amplifier with Chip Select
(CS). When CS is pulled high, the supply current drops
to 1 A (typical) and flows through the CS pin to VSS.
When this happens, the amplifier output is put into a
high-impedance state. By pulling CS low, the amplifier
is enabled. The CS pin has an internal 5 M
(typical)
pull-down resistor connected to VSS, so it will go low if
the CS pin is left floating. Figure 1-1, Figure 2-42 and
Figure 2-43 show the output voltage and supply current
response to a CS pulse.
The MCP635 is a dual amplifier with two CS pins; CSA
controls op amp A and CSB controls op amp B. These
op amps are controlled independently, with an enabled
quiescent current (IQ) of 2.5 mA/amplifier (typical) and
a disabled IQ of 1 A/amplifier (typical). The IQ seen at
the supply pins is the sum of the two op amps’ IQ; the
typical value for the MCP635’s IQ will be 2 A, 2.5 mA
or 5 mA when there are 0, 1 or 2 amplifiers enabled,
respectively.
The MCP639 is a quad amplifier with two CS pins; CSB
controls op amp B and CSD control s op amp D.
4.5
Power Supply
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm
for good high frequency performance. Surface mount,
multilayer ceramic capacitors, or their equivalent,
should be used.
These op amps require a bulk capacitor (i.e., 2.2 F or
larger) within 50 mm to provide large, slow currents.
Tantalum capacitors, or their equivalent, may be a good
choice. This bulk capacitor can be shared with other
nearby analog parts as long as crosstalk through the
supplies does not prove to be a problem.
4.6
High Speed PCB Layout
These op amps are fast enough that a little extra care
in the PCB (Printed Circuit Board) layout can make a
significant difference in performance. Good PC board
layout
techniques
will
help
you
achieve
the
performance shown in the specifications and Typical
Performance Curves; it will also help you minimize
EMC (Electro-Magnetic Compatibility) issues.
Use a solid ground plane. Connect the bypass local
capacitor(s) to this plane with minimal length traces.
This cuts down inductive and capacitive crosstalk.
Separate digital from analog, low speed from high
speed, and low power from high power. This will reduce
interference.
1.E+02
1.E+03
1.E+04
1.E+05
1
10
100
Noise Gain; GN (V/V)
M
ax
im
u
m
R
eco
mme
nd
ed
R
F
(
)
GN > +1 V/V
100
10k
100k
1k
CG = 10 pF
CG = 32 pF
CG = 100 pF
CG = 320 pF
CG = 1 nF
fF fGBWP 2GN2
, GN1 GN2
We need:
GN1
1RF RG
+
=
GN2
1CG CF
+
=
fF
12
R
FCF
=
fZ
fF GN1 GN2
=
Given:
fF fGBWP 4GN1
, GN1 GN2
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