參數(shù)資料
型號： MCV14ATI/SL
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14
封裝： 3.90 MM, PLASTIC, SOIC-4
文件頁數(shù)： 39/84頁
文件大?。?/td> 1007K
代理商： MCV14ATI/SL
MCV14A
DS41338B-page 42
Preliminary
2009 Microchip Technology Inc.
7.3.1
MCLR ENABLE
This Configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
VDD and the pin is assigned to be a I/O. See Figure 7-6.
FIGURE 7-6:
MCLR SELECT
7.4
Power-on Reset (POR)
The
MCV14A
device
incorporates
an
on-chip
Power-on Reset (POR) circuitry, which provides an
internal chip Reset for most power-up situations.
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the internal POR,
program the RB3/MCLR/VPP pin as MCLR and tie
through a resistor to VDD, or program the pin as RB3.
An internal weak pull-up resistor is implemented using
a transistor (refer to Table 11-5 for the pull-up resistor
ranges). This will eliminate external RC components
usually needed to create a Power-on Reset. A
maximum
rise time for
VDD is
specified.
See
When the device starts normal operation (exit the
Reset
condition),
device
operating
parameters
(voltage, frequency, temperature,...) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
parameters are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 7-7.
The Power-on Reset circuit and the Device Reset
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR to be high. After the
time-out period, which is typically 18 ms or 1 ms, it will
reset the Reset latch and thus end the on-chip Reset
signal.
A power-up example where MCLR is held low is shown
in Figure 7-8. VDD is allowed to rise and stabilize before
bringing MCLR high. The chip will actually come out of
Reset TDRT msec after MCLR goes high.
In Figure 7-9, the on-chip Power-on Reset feature is
being used (MCLR and VDD are tied together or the pin
is programmed to be RB3. The VDD is stable before the
start-up timer times out and there is no problem in get-
ting a proper Reset. However, Figure 7-10 depicts a
problem situation where VDD rises too slowly. The time
between when the DRT senses that MCLR is high and
when MCLR and VDD actually reach their full value, is
too long. In this situation, when the start-up timer times
out, VDD has not reached the VDD (min) value and the
chip may not function correctly. For such situations, we
recommend that external RC circuits be used to
achieve longer POR delay times (Figure 7-9).
For additional information, refer to Application Notes
AN522 “Power-Up Considerations” (DS00522) and
AN607 “Power-up Trouble Shooting” (DS00607).
RB3/MCLR/VPP
MCLRE
Internal MCLR
RBWU
Note:
When the device starts normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
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