參數(shù)資料
型號： MCV14ATI/SL
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14
封裝： 3.90 MM, PLASTIC, SOIC-4
文件頁數(shù)： 84/84頁
文件大?。?/td> 1007K
代理商： MCV14ATI/SL
2009 Microchip Technology Inc.
Preliminary
DS41338B-page 7
MCV14A
2.0
ARCHITECTURAL OVERVIEW
The high performance of the MCV14A device can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the MCV14A device uses a Harvard architecture
in which program and data are accessed on separate
buses. This improves bandwidth over traditional von
Neumann architectures where program and data are
fetched on the same bus. Separating program and
data memory further allows instructions to be sized
differently than the 8-bit wide data word. Instruction
opcodes are 12 bits wide, making it possible to have
all single-word instructions. A 12-bit wide program
memory access bus fetches a 12-bit instruction in a
single cycle. A two-stage pipeline overlaps fetch and
execution
of
instructions.
Consequently,
all
instructions (33) execute in a single cycle (200 ns @
20 MHz,
1
μs @ 4 MHz) except for program
branches.
Table 2-1 below lists memory supported by the
MCV14A device.
TABLE 2-1:
MCV14A MEMORY
The MCV14A device can directly or indirectly address
its register files and data memory. All Special Function
Registers (SFR), including the PC, are mapped in the
data memory. The MCV14A device has a highly orthog-
onal (symmetrical) instruction set that makes it possible
to carry out any operation, on any register, using any
Addressing mode. This symmetrical nature and lack of
“special optimal situations” make programming with the
MCV14A device simple, yet efficient. In addition, the
learning curve is reduced significantly.
The MCV14A device contains an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
The ALU is 8 bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two’s
complement in nature. In two-operand instructions, one
operand is typically the W (working) register. The other
operand is either a file register or an immediate
constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC) and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow and digit borrow out bit, respec-
tively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
A simplified block diagram is shown in Figure 2-2, with
the corresponding device pins described in Table 2-2.
Device
Program
Memory
Data Memory
Flash
(words)
SRAM
(bytes)
Flash
(bytes)
MCV14A
1024
67
64
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