參數(shù)資料
型號(hào): MCZ33970EG
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Dual Gauge Driver Integrated Circuit with Improved Damping Algorithms
中文描述: 雙計(jì)驅(qū)動(dòng)集成電路與改進(jìn)的阻尼算法
文件頁(yè)數(shù): 18/36頁(yè)
文件大?。?/td> 430K
代理商: MCZ33970EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
33970
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
The bits in
Table 12
are
write-only
.
RC12:RC11 (D12:D11) — These bits, along with RC3:RC0
(D3:D0) and RC4 (D4), determine the full step time and,
therefore, the rate at which the pointer will move during an
RTZ event. The values of D12:D11 determine the multiplier
(M) is used in equation (1) (refer to page
17
).
RC12:RC11 = M
00 = 1
01 = 2
10 = 4
11 = 8 (Not to be used for design)
RC10:RC5 (D10:D5) — These bits determine the value
preloaded into the RTZ integration accumulator to adjust the
detection threshold. Values range from -1 (00000000) to -
1099 (11111111) as shown in
Table 14
.
RC4 (D4) — This bit determines the RTZ blanking time
(
blanking
(
t)
).
0 = 512
μ
s
1 = 768
μ
s
RC3:RC0 (D3:D0) — These bits, along with RC12:RC11
(D12:D11) and RC4 (D4), determine the time variables used
to calculate the full step times with equations (1) or (2)
illustrated above. RC3:RC0 determines the
t time. The
t
values range from 0 (0000) to 61.440 ms (1111) and are
shown in
Table 13
. The default
t is 0 (0011).
Note
Equation (2) (refer to page
17
) is only used to
calculate the full step time if RC3:RC0 = 0000. Use
equation (1) for all other combinations of RC3:RC0.
SO Communication
When the
CS
pin is pulled low, the internal status register,
as configured with the PECCR command bits PE11:PE8, is
loaded into the output register and the data is clocked out
MSB (OD15) first. Following a
CS
transition 0 to 1, the device
determines if the shifted-in message was of a valid length (a
valid message length is one that is greater than 0 bits and a
multiple of 16 bits), and if so, latches the incoming data into
the appropriate registers.
At this time, the SO pin is tri-stated and the status register
is now able to accept new status information. Fault status
information will be latched and held until the Device Status
Output register is selected and it is clocked out via the SO. If
the message length was determined to be invalid, the fault
information will not be cleared and will be transmitted again
during the next valid SPI message. Pointer status information
bits (e.g., pointer position, velocity, and commanded position
status) will always reflect the real time state of the pointer.
Table 13. RTZCR Full Step Time
RC3
RC2
RC1
RC0
t (ms)
0
0
0
0
0
0
0
0
1
4.096
0
0
1
0
8.192
0
0
1
1
12.288
0
1
0
0
16.384
0
1
0
1
20.480
0
1
1
0
24.576
0
1
1
1
28.672
1
0
0
0
32.768
1
0
0
1
36.864
1
0
1
0
40.960
1
0
1
1
45.056
1
1
0
0
49.152
1
1
0
1
53.248
1
1
1
0
57.344
1
1
1
1
61.440
Table 14. RTZCR Accumulator Offset
RC10
RC9
RC8
RC7
RC6
RC5
Preload Value
(PV)
Initial Accumulator
Value = (-16 x PV) -1
0
0
0
0
0
0
0
-1
0
0
0
0
0
1
1
-17
0
0
0
0
1
0
2
-33
0
0
0
0
1
1
3
-49
0
0
0
1
0
0
4
-65
.
.
.
.
.
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1
1
1
1
1
1
63
-1009
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參數(shù)描述
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MCZ33972AEK/R2 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Multiple Switch Detection Interface with Suppressed Wake-up
MCZ33972AEKR2 功能描述:接口 - 專用 MULT SW DET SUP-WKUP RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59