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型號：	MD80C52XXX-25SC
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 25 MHz, MICROCONTROLLER, CDIP40
文件頁數(shù)：	515/1185頁
文件大?。?/td>	5451K
代理商：	MD80C52XXX-25SC

SAM9G45 [DATASHEET]

6438K–ATARM–12-Feb-13

Debug Communication Channel Support

The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel

of the ARM Processor and are driven by the In-circuit Emulator.

The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the

JTAG side and through the coprocessor 0 on the ARM Processor side.

As a reminder, the following instructions are used to read and write the Debug Communication Channel:

p14, 0, Rd, c1, c0, 0

Returns the debug communication data read register into Rd

MCRp14, 0, Rd, c1, c0, 0

Writes the value in Rd to the debug communication data write register.

The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been written by the

debugger but not yet read by the processor, and that the write register has been written by the processor and not

yet read by the debugger, are wired on the two highest bits of the status register DBGU_SR. These bits can gener-

ate an interrupt. This feature permits handling under interrupt a debug link between a debug monitor running on the

target system and a debugger.

Chip Identifier

The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension

ID). Both registers contain a hard-wired value that is read-only. The first register contains the following fields:

EXT - shows the use of the extension identifier register

NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size

ARCH - identifies the set of embedded peripherals

SRAMSIZ - indicates the size of the embedded SRAM

EPROC - indicates the embedded ARM processor

VERSION - gives the revision of the silicon

The second register is device-dependent and reads 0 if the bit EXT is 0.

ICE Access Prevention

The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface. This feature

is implemented via the register Force NTRST (DBGU_FNR), that allows assertion of the NTRST signal of the ICE

Interface. Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller.

On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access.

This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be

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