參數(shù)資料
型號(hào): MDS212
廠商: Zarlink Semiconductor Inc.
英文描述: 12-Port 10/100Mbps Ethernet Switch
中文描述: 12端口10/100Mbps以太網(wǎng)交換機(jī)
文件頁(yè)數(shù): 30/111頁(yè)
文件大?。?/td> 1609K
代理商: MDS212
MDS212
Data Sheet
30
Zarlink Semiconductor Inc.
5.2.1.5 VLAN MAC Association Table
The VLAN MAC Table (VLAN MCT) associates each port’s MAC address with its respective VLAN. The Table
comprises of 2048 entries, one entry per MAC address. Each VLAN MAC entry is mapped to each bit associated
with a VLAN specified by the VLAN Index.
The size of the Table is defined by two bits in the VTBP register and depends on the system configuration (e.g. the
number of VLANs supported in the system). Each entry may consist of 256, 128 or 64 bits (one bit per VLAN). The
total size of the VLAN MAC Table may be 16, 32, or 64KB. The VMACB field in the register VTBP specifies the
base address.
Note:
The VLAN MAC Table must be located at the 16K boundary.
5.2.2 Unmanaged System Memory Allocation
Since an unmanaged system does not support VLAN operation, the VLAN and VLAN MAC tables are not required.
Only the Frame Data Buffers, Transmission Queues, and HISC Mailing Lists are allocated in system memory.
Figure 5 - Memory Map of an Unmanaged System
5.3 The Frame Memory Interface
5.3.1 Local Memory Interface
Each frame within the MDS212 is allocated its own buffer memory. The primary function of the Frame Buffer
Memory is to provide a temporary buffering space for both received and transmitted frames, as well as frames
waiting in the transmission queue. The actual usage depends on the frame type to be transmitted, either unicast or
multicast and the relationship between the source and destination ports. The buffer memory also, contains other
control structures including stacks, queues, other control tables. The buffer memory may be configured for 128K,
256K, 512K, 1024K Bytes depending on the application of the system designer. The MDS212 local memory
interface supports up to 2M bytes of SBRAM.
The switch manager CPU initializes the local buffer memory during the switch initialization phase/process.
FDB
Frame Data Buffers
(1.5KB x # of frame buffers)
Transmission queues
(4x12=48 queues)
(each entry = 1DW)
(# entry of Queue = 128 to 1K)
HISC Mailing List
(# entry = 128 to 1K)
(each mail entry = 32 bytes to 64 bytes)
Byte
6
Byte
5
Byte
4
Byte
3
Byte
2
Byte
1
Byte
0
Byte
7
63
0
0
FDB block
must start from 0
Programmable Size
MAX
1/2MB, 1MB or 2MB
Programmable Size
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