參數(shù)資料
型號: MDS212
廠商: Zarlink Semiconductor Inc.
英文描述: 12-Port 10/100Mbps Ethernet Switch
中文描述: 12端口10/100Mbps以太網(wǎng)交換機(jī)
文件頁數(shù): 53/111頁
文件大小: 1609K
代理商: MDS212
MDS212
Data Sheet
53
Zarlink Semiconductor Inc.
14.2.4 MDS212 Data Structures For VLAN Implementation
Figure 18 - Data Structure Diagram
14.2.4.1 VLAN ID Table
The VLAN ID Table is used by Search Engine for unicast frames. The base address of this table is specified by
VIDB subfield in BIT[5:0] of VTBP register. The contents of this table are set up by the MDS212’s microcode
through the command of CPU software at the time of VLAN creation and deletion. The VLAN ID Table covers the
entire 4K VLAN ID space, and is used by the Search Engine to map the VLAN ID into an internal VLAN Index. It
also includes port membership and port tagging information for each VLAN. Each VLAN ID entry is 8 bytes long,
and the total size of the VLAN ID Table is 32KB. The VLAN ID table must be located at the 32K boundary.
Figure 19 - VLAN ID Table
FDB
Frame Data Buffers
Transmission queues
CPU/HISC Mailing List
VLAN ID Table
(4k entry, 8B/entry)
VLAN MAC Table
(2k entry, 256/128/64 bit)
Byte
5
4
Byte
6
Byte
Byte
3
Byte
2
Byte
1
Byte
0
Byte
7
63
0
Programmable Size
32KB
16, 32 or 64KB
MAX
1/2MV, 1MB,
or 2MB
FDB block must start from 0
External RAM
Programmable Size
(up to the number of supported VLAN)
P11
P23
31
29 28 27 26 25 24 23 22 21
20
30
19 18 17 16 15 14 13 12 11 10
9 8 7
6
5 4
3
2 1
Index[3:0]
Index[7:4]
C V
T
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P13
S
P12
0
4
Byte
Bit[1:0] P0
Bit [0]
Bit [1]
Bit[3:2] P1
....
Bit [26]
Bit [27]
Bit [31:28]
VLAN Status for Port 0
S
T
VLAN status for Port 1
This port is a member of this VLAN
Tagout
V
C
1st byte: VLAN Index [3:0], 2nd byte: VLAN Index [7:4]
VLAN is Valid
CPU is a member of this VLAN
0
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