參數(shù)資料
型號(hào): MDS212
廠商: Zarlink Semiconductor Inc.
英文描述: 12-Port 10/100Mbps Ethernet Switch
中文描述: 12端口10/100Mbps以太網(wǎng)交換機(jī)
文件頁數(shù): 40/111頁
文件大?。?/td> 1609K
代理商: MDS212
MDS212
Data Sheet
40
Zarlink Semiconductor Inc.
It provides independent 2 bit wide (di-bit) transmit and receive data paths.
It uses TTL signal levels, compatible with common digital CMOS ASIC processes.
Table 5 - RMII Specification Signals
10.0 The Control Bus
The CPU Interface, or Control Bus, provides the communication path between the system CPU and all other key
components within the switch (i.e. the HISC). It operates in two modes: managed mode, where it utilizes an
external CPU, and unmanaged mode, where an external CPU does not exist.
In Managed mode, the CPU Interface provides the communication path between the systems’ external CPU and
the HISC, Frame Buffer Memory (SRAM) or another MDS212. See Figure 10.
Figure 10 - CPU Interface Configuration in Managed Mode
In unmanaged mode, the CPU Interface provides the communication path between the Switch Devices
and Flash Memory, and between any two MDS212 Switches. See Figure 11.
Figure 11 - Control bus Configuration in Unmanaged Mode
Signal Name
Direction
(with respect to the PHY)
Direction
(with respect to the MAC)
REF_CLK
Input or Output
Synchronous clock reference for
receive, transmit and control interface
Carrier Sense/Receive Data Valid
Receive Data
Transmit Enable
Transmit Data
Receive Error
M[0:11]_CRS_DV
M[0:11]_RXD[1:0]
M[0:11]_TX_EN
M[0:11]_TXD[1:0]
M[0:11]_RX_ER
Input
Input
Output
Output
Input (Not required)
Control Bus
MDS212
MDS212
CPU
Flash
Memory
Control Bus
MDS212
MDS212
Flash
Memory
Primary DEV
Arbitrator
Secondary DEV
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