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參數(shù)資料
| 型號(hào)： | MH1S72CPG-12 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM |
| 中文描述： | 75497472位（1048576 - Word的72位）SynchronousDRAM |
| 文件頁數(shù)： | 17/47頁 |
| 文件大?。?/td> | 681K |
| 代理商： | MH1S72CPG-12 |
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MH1S72CPG-10,-12,-15
75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 47 )
17
MITSUBISHI
ELECTRIC
28.Mar.1997
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0089-3.0
Bank Activation and Precharge All (BL=4, CL=3)
CK
Command
A0-9
A10
BA
DQ
ACT
Xa
Xa
0
READ
Y
0
0
Qa0
Qa1
Qa2
Qa3
ACT
Xb
Xb
1
PRE
tRRD
tRCD
1
ACT
Xb
Xb
1
Precharge all
tRAS
tRP
OPERATION DESCRIPTION
BANK ACTIVATE
The SDRAM has two independent banks. Each bank is activated by the ACT command with
the bank address(BA). A row is indicated by the row address A10-0. The minimum activation
interval between one bank and the other bank is tRRD.
PRECHARGE
The PRE command deactivates indicated by BA. When both banks are active, the precharge
all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After tRP
from the precharge, an ACT command can be issued.
READ
After tRCD from the bank activation, a READ command can be issued. 1st output date is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when
the Burst Length is BL. The start address is specified by A7-0, and the address sequence of
burst data is defined by the Burst Type. A READ command may be applied to any active bank,
so the row precharge time(tRP) can be hidden behind continuous output data(in case of BL=8)
by interleaving the dual banks. When A10 is high at a READ command, the
auto-precharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited till the internal precharge is complete. The internal precharge start
timing depends on /CAD Latency. The next ACT command can be issued after tRP from the
internal precharge timing.
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