參數(shù)資料
型號： MH1S72CPG-12
廠商： Mitsubishi Electric Corporation
英文描述： 75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
中文描述： 75497472位（1048576 - Word的72位）SynchronousDRAM
文件頁數(shù)： 4/47頁
文件大?。?/td> 681K
代理商： MH1S72CPG-12
MH1S72CPG-10,-12,-15
75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 47 )
MITSUBISHI
ELECTRIC
28.Mar.1997
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0089-3.0
Serial Presence Detect Table
Byte
0
1
2
3
4
5
6
7
8
9
Function described
SPD enrty data
128
256 Bytes
SDRAM
A0-A10
A0-A7
1BANK
x72
0
LVTTL
10ns
12ns
15ns
8ns
8ns
9ns
SPD DATA(hex)
80
08
04
0B
08
01
48
00
01
A0
C0
F0
80
80
90
02
80
10
08
01
0F
02
06
01
01
00
06
F0
F0
FF
90
95
C0
78
78
78
6C
6C
78
1E
1E
28
14
18
1E
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
-10
-12
-15
-10
-12
-15
10
SDRAM Access from Clock
tAC for CL=3
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
SDRAM width,Primary DRAM
Error Checking SDRAM data width
Minimum Clock Delay,Back to Back Random Column Addresses
Burst Lengths Supported
# Banks on Each SDRAM device
CAS# Latency
CS# Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes:General
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
ECC
self refresh(15.625uS)
x16
x8
1
1/2/4/8
2bank
CL=1/2/3
0
0
non-buffered,non-registered
Precharge All,Auto precharge
-10
-12
-15
-10
-12
-15
-10
-12
-15
-10
-12
-15
-10
-12
-15
-10
-12
-15
15ns
15ns
20ns
9ns
9.5ns
12ns
30ns
30ns
30ns
27ns
27ns
30ns
30ns
30ns
40ns
20ns
24ns
30ns
24
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
25
SDRAM Cycle time(3rd highest CAS latency)
Cycle time for CL=1
26
SDRAM Access form Clock(3rd highest CAS latency)
tAC for CL=1
27
Precharge to Active Minimum
28
Row Active to Row Active Min.
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