參數(shù)資料
型號(hào)： MH1S72CPG-12
廠商： Mitsubishi Electric Corporation
英文描述： 75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
中文描述： 75497472位（1048576 - Word的72位）SynchronousDRAM
文件頁數(shù)： 6/47頁
文件大?。?/td> 681K
代理商： MH1S72CPG-12
MH1S72CPG-10,-12,-15
75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 47 )
6
MITSUBISHI
ELECTRIC
28.Mar.1997
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0089-3.0
PIN FUNCTION
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
CKE
Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S
(/S0 &/S2)
Input
Chip Select: When /S is high,any command means
No Operation.
/RAS,/CAS,/WE
Input
Combination of /RAS,/CAS,/WE defines basic commands.
A0-10
Input
A0-10 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-10.The Column
Address is specified by A0-7.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
BA
Input
Bank Address:BA is not simply BA.BA specifies the bank
to which a command is applied.BA must be set with
ACT,PRE,READ,WRITE commands
Data in and Data out are referenced to the rising edge of
CK
Check bit in and Check bit out are referenced to the
rising edge of CK
DQ0-63
Input/Output
DQMB0-7
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
Vdd,Vss
Power Supply Power Supply for the memory mounted module.
SLA
SDA
Input
Output
Serial clock for serial PD
Serial data for serial PD
CK
(CK0)
CB0-7
Input/Output
相關(guān)PDF資料
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