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參數(shù)資料
| 型號： | MH1S72CPG-12 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM |
| 中文描述： | 75497472位（1048576 - Word的72位）SynchronousDRAM |
| 文件頁數(shù)： | 21/47頁 |
| 文件大?。?/td> | 681K |
| 代理商： | MH1S72CPG-12 |
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MH1S72CPG-10,-12,-15
75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 47 )
21
MITSUBISHI
ELECTRIC
28.Mar.1997
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0089-3.0
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the same or the other bank. Read
to PRE interval is minimum 1 CK. A PRE command disables the data output, depending on
the /CAS Latency. The figure below shows examples, when the dataout is terminated.
Read Interrupted by Precharge (BL=4)
CK
Command
DQ
READ
PRE
Q0
Q2
Q3
Q1
Command
DQ
READ
Q0
Q1
Command
DQ
READ
PRE
Q0
Q1
Command
DQ
READ
PRE
Q0
Q1
Command
DQ
READ
PRE
Q0
Q2
Q3
Q1
Command
DQ
READ
PRE
Q0
Q1
PRE
Q2
Q3
CL=4
CL=3
CL=2
Comman
d
DQ
REA
D
PRE
Q
0
Q
2
Q
3
Q
1
Comman
d
DQ
REA
D
PR
E
Q
0
Q
1
CL=
1
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