參數(shù)資料
型號： MH1S72CPG-15
廠商： Mitsubishi Electric Corporation
英文描述： 75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
中文描述： 75497472位（1048576 - Word的72位）SynchronousDRAM
文件頁數(shù)： 15/47頁
文件大?。?/td> 681K
代理商： MH1S72CPG-15
MH1S72CPG-10,-12,-15
75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 47 )
15
MITSUBISHI
ELECTRIC
28.Mar.1997
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0089-3.0
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP
condition at the inputs.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500é s.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which may
be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is
ready for new command.
BA A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
LTMODE
BT
BL
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BURST
LENGTH
BT= 0
1
2
4
8
R
R
R
R
BT= 1
1
2
4
8
R
R
R
R
0
1
BURST
TYPE
SEQUENTIAL
INTERLEAVED
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
LATENCY
MODE
/CAS LATENCY
1
2
3
R
R
R
R
R
R:Reserved for Future Use
/S
/RAS
/CAS
/WE
BA, A10 -A0
CK
V
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