參數(shù)資料
型號(hào): MH1S72CPG-15
廠商: Mitsubishi Electric Corporation
英文描述: 75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
中文描述: 75497472位(1048576 - Word的72位)SynchronousDRAM
文件頁數(shù): 31/47頁
文件大?。?/td> 681K
代理商: MH1S72CPG-15
MH1S72CPG-10,-12,-15
75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 47 )
31
MITSUBISHI
ELECTRIC
28.Mar.1997
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0089-3.0
AC TIMING REQUIREMENTS (Component SDRAM)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
CK
Signal
1.4V
1.4V
Any AC timing is
referenced to the input
signal crossing through
1.4V.
Max.
Limits
-12
Min.
30
15
12
Symbol Parameter
-15
Unit
Max.
Min.
Max.
30
20
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tCLK
CK cycle time
tCH
tCL
tT
tIS
tIH
tRC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tSRX
tREF
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
Mode Register Set Cycle time
Self Refresh Exit time
Refresh Interval time
4
4
1
3
1
4
4
1
3
10
10
1.5
120
30
80 10000
40
15
30
30
15
100
30
70 10000
30
12
24
24
12
65.6
65.6
CL=1
CL=2
CL=3
Min.
30
15
10
-10
4
4
1
3
1
10
90
30
60 10000
30
10
20
20
12
65.6
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