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參數(shù)資料
| 型號： | MH32S72DBFA-8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| 中文描述： | 2415919104位（33554432 - Word的72位）同步動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 53/56頁 |
| 文件大?。?/td> | 917K |
| 代理商： | MH32S72DBFA-8 |
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2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MH32S72AQJA-7, -8
17/Mar./2000
MIT-DS-0371-0.2
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
Serial Presence Detect Table I
Byte
0
1
2
3
4
5
6
7
8
9
Function described
SPD enrty data
128
256 Bytes
SDRAM
A0-A11
SPD DATA(hex)
80
08
04
0C
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL).
A0-A10
1BANK
x72
0B
01
48
0
00
01
LVTTL
A0
Cycle time for CL=3
10
SDRAM Access from Clock
tAC for CL=3
6ns
60
11
12
13
14
15
16
17
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
SDRAM width,Primary DRAM
Error Checking SDRAM data width
ECC
02
self refresh(15.625uS)
80
x4
x4
04
04
Minimum Clock Delay,Back to Back Random Column Addresses
1
01
8F
04
Burst Lengths Supported
# Banks on Each SDRAM device
1/2/4/8/Full page
4bank
18
CAS# Latency
2/3
06
19
20
CS# Latency
Write Latency
0
0
01
01
21
22
SDRAM Module Attributes
SDRAM Device Attributes:General
buffered,registered
Precharge All,Auto precharge
Write1/Read Burst
1F
0E
23
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
13ns
D0
24
SDRAM Access form Clock(2nd highest CAS latency)
7ns
70
tAC for CL=2
25
SDRAM Cycle time(3rd highest CAS latency)
N/A
00
N/A
00
26
SDRAM Access form Clock(3rd highest CAS latency)
27
Precharge to Active Minimum
20ns
14
28
Row Active to Row Active Min.
20ns
14
10ns
-8
-8
-7
10ns
A0
6ns
60
-7
29
RAS to CAS Delay Min
20ns
14
30
Active to Precharge Min
50ns
32
53
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MH32S72PHB-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2415919104-BIT (33554432 - WORD BY 72-BIT)SynchronousDRAM |
| MH32S72PHB-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH32S72PHB-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2415919104-BIT (33554432 - WORD BY 72-BIT)SynchronousDRAM |
| MH32S72PHB-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2415919104-BIT (33554432 - WORD BY 72-BIT)SynchronousDRAM |
| MH32S72QJA-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2415919104-BIT ( 33554432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
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