參數(shù)資料
型號： MH4S64CBMD-15B
廠商： Mitsubishi Electric Corporation
英文描述： 268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
中文描述： 268435456位（4194304字，64位）SynchronousDRAM
文件頁數(shù)： 23/55頁
文件大?。?/td> 586K
代理商： MH4S64CBMD-15B
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( 23
MITSUBISHI
ELECTRIC
29.Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.5
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of the same or the other bank.
Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
A10
DQ
Write
Yi
0
00
Write
Yk
0
10
Dai0
Daj0
Daj1
Dbk0
Write
Yj
0
00
Dbk1 Dbk2
Write
Yl
0
00
Dal0
Dal1
Dal2
Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank.
Random column access is allowed. WRITE to READ interval is minimum 1 CK. The
input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CK
Command
A10
DQ
Write
Yi
0
00
Qaj0
READ
Yj
0
00
Qaj1
Dai0
Dbk0 Dbk1
DQMB0-7
Write
Yk
0
10
READ
Yl
0
00
Qbl0
A0-9
BA0,1
A0-9,11
BA0,1
A11
A11
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