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參數(shù)資料
| 型號(hào)： | MH4S64CBMD-15B |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM |
| 中文描述： | 268435456位（4194304字，64位）SynchronousDRAM |
| 文件頁(yè)數(shù)： | 31/55頁(yè) |
| 文件大?。?/td> | 586K |
| 代理商： | MH4S64CBMD-15B |
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MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 55 )
31
MITSUBISHI
ELECTRIC
29.Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.5
AC TIMING REQUIREMENTS
(SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
CK
Signal
1.4V
1.4V
Any AC timing is
referenced to the input
signal crossing through
1.4V.
Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns should
be added to the parameter.
Limits
-8
Min.
Symbol Parameter
-7
Unit
Min.
Max.
tCLK
CK cycle time
ns
ns
tCH
tCL
tT
tIS
tIH
tRC
tRCD
tRAS
tRP
tWR
tRRD
tCCD
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
Col to Col Delay time
3
3
1
2
1
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
70
20
50
20
10
20
10
100K
tRSC
tSRX
tREF
Mode Register Set Cycle time
Self Refresh Exit time
Refresh Interval time
20
10
ns
ns
ms
64
Max.
3
3
1
2
1
13
10
10
70
20
50
20
10
20
10
100K
20
10
64
CL=2
CL=3
-10
Min.
Max.
4
4
1
3
1
15
10
10
90
30
60
30
10
20
10
100K
20
10
64
Note
1
1
1
1
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| MH4S64CZTJ-15 | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM |
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