參數(shù)資料
型號(hào)： MH64D72KLH-75
廠商： Mitsubishi Electric Corporation
英文描述： 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
中文描述： 4831838208位（67108864 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊
文件頁(yè)數(shù)： 18/38頁(yè)
文件大?。?/td> 326K
代理商： MH64D72KLH-75
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH64D72KLG-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0389-1.1
20.Nov.2000
Preliminary Spec.
Some contents are subject to change without notice.
18
AC TIMING REQUIREMENTS
(Component Level)
(Ta=0 ~ 70 , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
C
ns
15
10
15
10
CL=2
ns
15
8
15
7.5
CL=2.5
19
19
20
ns
+0.6
+0.5
DQS-DQ Skew(for DQS and all DQ signals)
tDQSA
ns
min(tCL,t
CH
min(tCL,
tCH
CLK half period
tHP
tCK
0.55
0.45
0.55
0.45
CLK Low level width
tCL
CLK cycle time
tCK
16
15
14
14
AC Characteristics
-10
-75
1.1
0.9
1.1
0.9
0.6
0.4
0.6
0.4
1.2
0.9
1.2
0.9
0.25
0.25
0.6
0.4
0.6
0.4
0
0
15
15
0.2
0.2
0.2
0.2
0.35
0.35
0.35
0.35
1.25
0.75
1.25
0.75
tHP-1.0
tHP-0.75
+0.6
+0.5
+0.8
-0.8
+0.75
-0.75
+0.8
-0.8
+0.75
-0.75
2
1.75
tCK
tCK
ns
ns
tCK
tCK
ns
ns
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
0.6
0.5
0.6
0.5
tCK
0.45
0.55
0.45
+0.8
-0.8
+0.75
-0.75
+0.8
-0.8
+0.75
-0.75
Max.
Min.
Max.
Min.
Parameter
0.55
Read preamble
tRPRE
Read postamble
tRPST
tWPRE
Write preamble
tWPST
Write postamble
tWPRES
Write preamble setup time
Input Hold time (address and control)
tIH
tIS
Input Setup time (address and control)
tMRD
Mode Register Set command cycle time
tDSH
DQS falling edge hold time from CLK
tDSS
DQS falling edge to CLK setup time
tDQSL
DQS input Low level width
tDQSH
DQS input High level width
tDQSS
Write command to first DQS latching transition
tQH
DQ/DQS output hold time from DQS
tDQSQ
DQS-DQ Skew(for DQS and associated DQ signals)
Data-out-low impedance time from CLK//CLK
tLZ
tHZ
Data-out-high impedance time from CLK//CLK
tDIPW
DQ and DM input pulse width (for each input)
Input Hold time(DQ,DM)
Input Setup time (DQ,DM)
tDS
tDH
tCH
CLK High level width
ns
DQ Output Valid data delay time from CLK//CLK
tDQSCK
DQ Output Valid data delay time from CLK//CLK
ns
tAC
Notes
Unit
Symbol
O
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