參數(shù)資料
型號(hào): MH64D72KLH-75
廠商: Mitsubishi Electric Corporation
英文描述: 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
中文描述: 4831838208位(67108864 - Word的72位),雙數(shù)據(jù)速率同步DRAM模塊
文件頁(yè)數(shù): 24/38頁(yè)
文件大小: 326K
代理商: MH64D72KLH-75
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH64D72KLG-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0389-1.1
20.Nov.2000
Preliminary Spec.
Some contents are subject to change without notice.
24
READ with Auto-Precharge (BL=8, CL=2(Discrete))
Module input and output timing.
Command
A0-9,11-12
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
1
00
ACT
Xb
Xb
00
Internal precharge start
(BL/2+1 in case of Module)
tRCD
tRP
BL/2 + tRP
BL/2
DQS
/CLK
CLK
Q a
Q a
Q a
Q a
Q a
Q a
Q a
Q a
READ Auto-Precharge Timing (BL=8)
Command
ACT
READ
DQ
CL=2.5
BL/2
DQ
CL=2
Q a
/CLK
CLK
Q a
Q a
Q a
Q a
Q a
Q a
Q a
Q a
Q a
Q a
Q a
Q a
Q a
Q a
Q a
Module input and output timing.
Discrete
Internal Precharge Start Timing
(In case of module, Precharge start at BL/2+1)
CL=3.5
CL=3
Module
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