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參數(shù)資料
| 型號(hào)： | MIP7365-450F17I |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 450 MHz, MICROPROCESSOR, CQFP208 |
| 封裝： | 1.20 X 1.20 MM, CERAMIC, QFP-208 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 285K |
| 代理商： | MIP7365-450F17I |
SCD7365 Rev B
FEATURES
Upscreened PMC-Sierra RM7065C
Military and Industrial Grades Available
Dual issue symmetric superscalar microprocessor with instruction prefetch optimized for system level
price/performance
o 450MHz operating frequency
High-performance system interface
o Multiplexed address/data bus (SysAD) supports 2.5V, 3.3V I/O logic
o Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
o Support for 64-bit or 32-bit external agents
Integrated primary and secondary caches
o All are 4-way set associative with 32-byte line size
o 16-Kbytes instruction, 16-Kbytes data, 256-Kbytes on-chip secondary
o Per line cache locking in primaries and secondary
o Fast Packet Cache increases system efficiency in networking applications
High-performance floating-point unit — 1600MFLOPS maximum
o Single cycle repeat rate for common single-precision operations and some double-precision operations
o Single cycle repeat rate for single-precision combined multiply-add operations
o Two cycle repeat rate for double-precision multiply and double-precision combined multiply-add operations
MIPS IV superset instruction set architecture
o Data PREFETCH instruction allows the processor to overlap cache miss latency and instruction execution
o Single-cycle floating-point multiply-add
Integrated memory management unit
o Fully associative joint TLB (shared by I and D translations)
o 64/48 dual entries map 128/96 pages
o Variable page size
Embedded application enhancements
o Specialized DSP integer Multiply-Accumulate instructions, (MAD/MADU) and three-operand multiply
instruction (MUL)
o I&D Test/Break-point (Watch) registers for emulation & debug
o Performance counter for system and software tuning & debug
o Fourteen fully prioritized vectored interrupts — 10 external, 2 internal, 2 software
Fully static CMOS design with dynamic power down logic
216-EPad LQFP 24x24mm are pin compatible with the RM7965 and RM5261A EPad products
NOTE: 216-Enhanced Pad package, EPad MIPS64 and Fast Packet Cache are Trademarks of PMC-Sierra
MIP7365
Standard Products
January 11, 2007
64-Bit Superscaler Microprocessor
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PDF描述 |
|---|---|
| MIP7365-450B1M | 64-BIT, 450 MHz, MICROPROCESSOR, PBGA256 |
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| MK1574-01ASTR | 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
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| MK2308S-2ILF | 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
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