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參數(shù)資料
| 型號： | MIP7365-450F17I |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 450 MHz, MICROPROCESSOR, CQFP208 |
| 封裝： | 1.20 X 1.20 MM, CERAMIC, QFP-208 |
| 文件頁數(shù)： | 16/16頁 |
| 文件大小： | 285K |
| 代理商： | MIP7365-450F17I |
9
SCD7365 Rev B 1/11/07
Aeroflex Plainview
AC CHARACTERISTICS
CAPACITIVE LOAD DERATION
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNITS
Mode
CLD
Load Derate
-
2
ns/25pF
LVTTL
CLOCK PARAMETERS
PARAMETER
SYMBOL
TEST CONDITIONS
BUS SPEED
UNITS
LVTTL
MIN
MAX
SysClock High
tSCHigh
Transition < 2ns
3
-
ns
SysClock Low
tSCLow
Transition < 2ns
3
-
ns
SysClock Frequency1
33.3
133
MHz
SysClock Period
tSCP
7.5
30
ns
Clock Jitter for SysClock
tJitterIn
-±150
ps
SysClock Rise Time
tSCRise
-2
ns
SysClock Fall Time
tSCFall
-2
ns
ModeClock Period
tModeCKP
-
256
ns
JTAG Clock Period
tJTAGCKP
4-
ns
Notes:
1. Operation of the MIP7365 is only guaranteed with the Phase Loop enabled.
SYSTEM INTERFACE PARAMETERS
PARAMETER1
SYM
TEST CONDITIONS5,6
I/O TYPE
UNITS
LVTTL I/O
MIN
MAX
Data Output2,6,7
tDO
LVTTL (VccIO = 3.3V): mode[14:13] = 10 (fastest)
0.75
4.5
ns
LVTTL (VccIO = 3.3V): mode[14:13] = 01 (slowest)
0.75
5.5
ns
Data Setup4
tDS
tRISE = See above table
2.5
-
ns
Data Hold4
tDH
tFALL= See above table
1.0
-
ns
Notes
1. In LVTTL mode, timings are measured from 0.425 x VccIO of clock to 0.425 x VccIO of signal for 3.3V I/O, and from 0.48 x VccIO
of clock to 0.48 x VccIO of signal for 2.5V I/O. Input Rise/Fall time = 1V/1ns.
2. Capacitive load for all LVTTL maximum output timings is 50 pF. Minimum output timings are for theoretical no load conditions -
untested.
4. Data Output timing applies to all signal pins whether tristate I/O or output only.
5. Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
6. Only mode 14:13 = 01 is tested and guaranteed.
7. Data shown is for 3.3 V I/O. For 2.5 V I/O: derate tDO min by 0.25 nS, and tDO max by 0.5 nS. Mode setting is mode [14:13] = 10
(fastest) or 01 (slowest).
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