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參數(shù)資料
| 型號： | MK2069-04GILF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK SYNTHESIZER 56-TSSOP |
| 標準包裝： | 34 |
| 類型： | 時鐘同步器 |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 56-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1254 (CN2011-ZH PDF) |
| 其它名稱： | 800-1783 800-1783-5 800-1783-ND |
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
5
MK2069-04
REV J 051310
Application Information
The MK2069-04 is a mixed analog / digital integrated circuit
that is sensitive to PCB (printed circuit board) layout and
external component selection. Used properly, the device will
provide the same high performance expected from a
canned VCXO-based hybrid timing device, but at a lower
cost. To help avoid unexpected problems, the guidance
provided in the sections below should be followed.
Setting VCLK Output Frequency
The frequency of the VCLK output is determined by the
following relationship:
Where:
FV Divider = 1 to 4096
RPV Divider = 1 or 8
RV Divider = 2 to 4097
Because the RPV divider inherently has a higher speed of
operation than the RV divider, the RPV divider should be set
to 8 when this factor is included in the RPV x RV divisor
combination.
VCLK output frequency range is set by the allowable
frequency range of the external VCXO crystal and by the
internal VCXO divider selections:
Where:
F(VCXO) = F(External Crystal) = 8 to 27 MHz
SV Divider = 1,2,4,6,8,10,12 or 16
A higher crystal frequency will generally produce lower
phase noise and therefore is preferred. A crystal frequency
between 13.5 MHz and 27 MHz is recommended.
Because VCLK is generated by the external crystal, the
tracking range of VCLK in a given configuration is limited by
the pullable range of the crystal. This is guaranteed to be
±115 ppm minimum. This tracking range in ppm also applies
to the input clock and all clock outputs if the device is to
remain frequency locked to the input, which is required for
normal operation.
Setting TCLK Output Frequency
The clock frequency of TCLK is determined by:
Where:
FT Divider = 2, 4, 6, 8, 10, 12, 14 or 16
The frequency range of TCLK is set by the operational range
of the internal VCO circuit and the output divider selections:
Where:
f(VCO) = 40 to 320 MHz
ST Divider = 2,4,8 or 16
A higher VCO frequency will generally produce lower phase
noise and therefore is preferred.
MK2069-04 Loop Response and JItter
Attenuation Characteristics
The MK2069-04 will reduce the transfer of phase jitter
existing on the input reference clock to the output clock. This
operation is known as jitter attenuation. The low-pass
frequency response of the VCXO PLL loop is the
mechanism that provides input jitter attenuation. Clock jitter,
more accurately called phase jitter, is the overall instability
of the clock period which can be measured in the time
domain using an oscilloscope, for instance. Jitter is
comprised of phase noise which can be represented in the
frequency domain. The phase noise of the input reference
clock is attenuated according to the VCXO PLL low-pass
frequency response curve. The response curve, and thus
the jitter attenuation characteristics, can be established
through the selection of external MK2069-04 passive
components and other device setting as explained in the
following section.
f(VCLK)
FV Divider
RPV Divider
RV Divider
×
-------------------------------------------------------------------
f(ICLK)
×
=
f(VCLK)
fVCXO
()
SV Divider
-----------------------
=
f(TCLK)
FT Divider
f(VCLK)
×
=
f(TCLK)
f(VCO)
ST Divider
-----------------------
=
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MK2069-04GILFTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2069-04GITR | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MK206N 454634/1/MK | 制造商:NSF (CONTROLS) 功能描述:WAFER MK 2POLE 6 POS 制造商:NSF (CONTROLS) 功能描述:WAFER, MK, 2POLE, 6 POS 制造商:NSF (CONTROLS) 功能描述:WAFER, MK, 2POLE, 6 POS; For Use With:Rotary Switches; No. of Poles:2; No. of Positions:6; SVHC:No SVHC (19-Dec-2012); Contact Current @ Contact Voltage AC Max:500mA; Contact Current AC Max:5A; Contact Current DC Max:5A; Contact ;RoHS Compliant: Yes |
| MK206S 454634MK | 制造商:NSF (CONTROLS) 功能描述:WAFER MK 2POLE 6 POS 制造商:NSF (CONTROLS) 功能描述:WAFER, MK, 2POLE, 6 POS 制造商:NSF (CONTROLS) 功能描述:WAFER, MK, 2POLE, 6 POS; No. of Poles:2; No. of Positions:6; SVHC:No SVHC (19-Dec-2012); Contact Current @ Contact Voltage AC Max:500mA; Contact Current AC Max:5A; Contact Current DC Max:5A; Contact Current Rating:5A; Contact ;RoHS Compliant: Yes |
| MK20-B-100W | 功能描述:近程傳感器 1 Form A Cylindrical Term. RoHS:否 制造商:Vishay Semiconductors 感應方式:Optical 感應距離:1 mm to 200 mm 電源電壓:2.5 V to 3.6 V 安裝風格:SMD/SMT 輸出配置:Digital 最大工作溫度:+ 85 C 最小工作溫度:- 25 C 系列:VCNL3020 |
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