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參數(shù)資料
| 型號(hào)： | MK2069-04GILF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK SYNTHESIZER 56-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 34 |
| 類型： | 時(shí)鐘同步器 |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1254 (CN2011-ZH PDF) |
| 其它名稱： | 800-1783 800-1783-5 800-1783-ND |
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
10
MK2069-04
REV J 051310
the following relationship:
(LD Threshold) = 0.6 x R x C
Where:
1 k
Ω< R < 1 MΩ (to avoid excessive noise or leakage)
C > 50 pF (to avoid excessive error due to stray
capacitance, which can be as much as 10 pF
including Cin of LDC)
Lock Detector Application example:
The desired maximum allowable loop phase error for a
generated 19.44 MHz clock is 100UI which is 5.1
μs.
Solution: 5.1
μs = (0.001 μF) x (8.5 kΩ)
Under ideal conditions, where the VCXO is phase- locked to
a low-jitter reference input, loop phase error is typically
maintained to within a few nanoseconds.
Lock Detection Circuit Diagram
If the lock detection circuit is not used, the LDR output may
remain unconnected, however the LDC input should be tied
high or low. If the PCB was designed to accommodate the
RLD and CLD components but the LD output will not be
used, RLD can remain unstuffed and CLD can be replaced
with a resistor (< 10 kohm).
Power Supply Considerations
As with any integrated clock device, the MK2069-04 has a
special set of power supply requirements:
The feed from the system power supply must be filtered
for noise that can cause output clock jitter. Power supply
noise sources include the system switching power supply
or other system components. The noise can interfere with
device PLL components such as the VCO or phase
detector.
Each VDD pin must be decoupled individually to prevent
power supply noise generated by one device circuit block
from interfering with another circuit block.
Clock noise from device VDD pins must not get onto the
PCB power plane or system EMI problems may result.
This above set of requirements is served by the circuit
illustrated in the Recommended Power Supply Connection
(next page). The main features of this circuit are as follows:
Only one connection is made to the PCB power plane.
The capacitors and ferrite chip (or ferrite bead) on the
common device supply form a lowpass ‘pi’ filter that
remove noise from the power supply as well as clock
noise back toward the supply. The bulk capacitor should
be a tantalum type, 1
μF minimum. The other capacitors
should be ceramic type.
The power supply traces to the individual VDD pins
should fan out at the common supply filter to reduce
interaction between the device circuit blocks.
The decoupling capacitors at the VDD pins should be
ceramic type and should be as close to the VDD pin as
possible. There should be no via’s between the
decoupling capacitor and the supply pin.
Lo c k D e te c tio n C irc uit
Lo c k
Q u a lific a tio n
C ounte r
(8 up , 1 dow n)
VC XO
Ph a s e
De te c to r
Erro r
Ou tp u t
LD
LD C
LD R
RL D
CL D
R ESET
FV
Div id e r
Ou tp u t
OE L
Input Th re s hold
s e t to V D D /2
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參數(shù)描述 |
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| MK2069-04GILFTR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2069-04GITR | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK206N 454634/1/MK | 制造商:NSF (CONTROLS) 功能描述:WAFER MK 2POLE 6 POS 制造商:NSF (CONTROLS) 功能描述:WAFER, MK, 2POLE, 6 POS 制造商:NSF (CONTROLS) 功能描述:WAFER, MK, 2POLE, 6 POS; For Use With:Rotary Switches; No. of Poles:2; No. of Positions:6; SVHC:No SVHC (19-Dec-2012); Contact Current @ Contact Voltage AC Max:500mA; Contact Current AC Max:5A; Contact Current DC Max:5A; Contact ;RoHS Compliant: Yes |
| MK206S 454634MK | 制造商:NSF (CONTROLS) 功能描述:WAFER MK 2POLE 6 POS 制造商:NSF (CONTROLS) 功能描述:WAFER, MK, 2POLE, 6 POS 制造商:NSF (CONTROLS) 功能描述:WAFER, MK, 2POLE, 6 POS; No. of Poles:2; No. of Positions:6; SVHC:No SVHC (19-Dec-2012); Contact Current @ Contact Voltage AC Max:500mA; Contact Current AC Max:5A; Contact Current DC Max:5A; Contact Current Rating:5A; Contact ;RoHS Compliant: Yes |
| MK20-B-100W | 功能描述:近程傳感器 1 Form A Cylindrical Term. RoHS:否 制造商:Vishay Semiconductors 感應(yīng)方式:Optical 感應(yīng)距離:1 mm to 200 mm 電源電壓:2.5 V to 3.6 V 安裝風(fēng)格:SMD/SMT 輸出配置:Digital 最大工作溫度:+ 85 C 最小工作溫度:- 25 C 系列:VCNL3020 |
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