參數(shù)資料
型號(hào)： MK60DX256ZVLL10
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 1312/1809頁(yè)
文件大?。?/td> 0K
描述： IC ARM CORTEX MCU 256KB 100LQFP
標(biāo)準(zhǔn)包裝： 450
系列： Kinetis
核心處理器： ARM? Cortex?-M4
芯體尺寸： 32-位
速度： 100MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，I²C，IrDA，SDHC，SPI，UART/USART，USB，USB OTG
外圍設(shè)備： DMA，I²S，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 66
程序存儲(chǔ)器容量： 256KB（256K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.71 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 25x16b，D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 100-LQFP
包裝： 托盤
MCG_S field descriptions (continued)
Field
Description
While the PLL clock is locking to the desired frequency, the MCG PLL clock (MCGPLLCLK) will be gated
off until the LOCK bit gets asserted. If the lock status bit is set, changing the value of the PRDIV [4:0] bits
in the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock status bit to clear and stay
cleared until the PLL has reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN =0 also
causes the lock status bit to clear and stay cleared until the Stop mode is exited and the PLL has
reacquired lock. Any time the PLL is enabled and the LOCK bit is cleared, the MCGPLLCLK will be gated
off until the LOCK bit is asserted again.
0
PLL is currently unlocked.
1
PLL is currently locked.
5
PLLST
PLL Select Status
This bit indicates the clock source selected by PLLS . The PLLST bit does not update immediately after a
write to the PLLS bit due to internal synchronization between clock domains.
0
Source of PLLS clock is FLL clock.
1
Source of PLLS clock is PLL clock.
4
IREFST
Internal Reference Status
This bit indicates the current source for the FLL reference clock. The IREFST bit does not update
immediately after a write to the IREFS bit due to internal synchronization between clock domains.
0
Source of FLL reference clock is the external reference clock.
1
Source of FLL reference clock is the internal reference clock.
3–2
CLKST
Clock Mode Status
These bits indicate the current clock mode. The CLKST bits do not update immediately after a write to the
CLKS bits due to internal synchronization between clock domains.
00
Encoding 0 — Output of the FLL is selected (reset default).
01
Encoding 1 — Internal reference clock is selected.
10
Encoding 2 — External reference clock is selected.
11
Encoding 3 — Output of the PLL is selected.
1
OSCINIT
OSC Initialization
This bit, which resets to 0, is set to 1 after the initialization cycles of the crystal oscillator clock have
completed. After being set, the bit is cleared to 0 if the OSC is subsequently disabled. Refer to the OSC
module's detailed description for more information.
0
IRCST
Internal Reference Clock Status
The IRCST bit indicates the current source for the internal reference clock select clock (IRCSCLK). The
IRCST bit does not update immediately after a write to the IRCS bit due to internal synchronization
between clock domains. The IRCST bit will only be updated if the internal reference clock is enabled,
either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN] bit .
0
Source of internal reference clock is the slow clock (32 kHz IRC).
1
Source of internal reference clock is the fast clock (2 MHz IRC).
Memory Map/Register Definition
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
550
Freescale Semiconductor, Inc.
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