參數(shù)資料
型號: ML6401
廠商: Fairchild Semiconductor Corporation
英文描述: 8-Bit 20MSa/s Video A/D Converter(8位20MSa/s視頻A/D轉(zhuǎn)換器)
中文描述: 8位20MSa / s的視頻A / D轉(zhuǎn)換器(8位20MSa /秒視頻的A / D轉(zhuǎn)換器)
文件頁數(shù): 1/12頁
文件大小: 233K
代理商: ML6401
1
GENERAL DESCRIPTION
The ML6401 is a single-chip 8-bit 20 MSa/s BiCMOS
Video A/D Converter IC, incorporating a differential input
track and hold, clock generation circuitry, and reference
voltage.
The input track and hold consists of a low (4pF)
capacitance input and a fast settling operational amplifier.
The A/D conversion is accomplished through a pipeline
approach, reducing the number of required comparators
and latches. The non-over-lapping clocks required for this
architecture are all internally generated. Clock generation
circuitry requires only one 50% duty cycle clock input.
The use of error correction throughout the A/D converter
improves DNL. All bias voltages and currents required by
the A/D converter are internally generated. The digital
outputs are three-stateable.
FEATURES
I
5.0V ±10% single supply operation
I
Internal reference voltage
I
Power dissipation less than 200mW typical
I
Replaces TMC1175MC20 and AD775JR
I
Functionally compatible to Sony CXD1175AM/AP
I
Low input capacitance track and hold: 4pF
I
Onboard non-overlapping clock generation to
minimize external components
I
3-state outputs and no missing codes
I
150MHz input track and hold
BLOCK DIAGRAM
(Pin Configuration Shown is for S24 Version)
January 1998
ML6401
8-Bit 20MSa/s A/D Converter
DIGITAL
ERROR
CORRECTION
OE
D7
D6
D5
D4
D3
D2
D1
D0
VDDO
VDDA
VDDA
VDDA
VDDD
GNDO
2
GNDD
24
GNDA
20
GNDA
21
CLK
CLOCK GENERATOR
SUB
DAC
AMP
SUB
DAC
AMP
A/D 3
A/D 2
A/D 1
VIN+
VIN–
INTERNAL
REFERENCES
1.5V
1.0V
VIN
–BIAS
VREFOUT
VREFIN
1
10
9
8
7
6
5
4
3
22
16
19
23
17
12
15
18
14
11
13
150MHz
T & H
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