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參數(shù)資料
| 型號(hào)： | ML6401 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 8-Bit 20MSa/s Video A/D Converter(8位20MSa/s視頻A/D轉(zhuǎn)換器) |
| 中文描述： | 8位20MSa / s的視頻A / D轉(zhuǎn)換器（8位20MSa /秒視頻的A / D轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大小： | 233K |
| 代理商： | ML6401 |
6
ML6401
INPUT COUPLING
Figures 3 and 4 illustrate two simple means of connecting
AC and DC coupled signals into the ML6401-1.
CXD1175 REPLACEMENT
The 24-pin ML6401-1 is pin compatible with the Sony
CXD1175 since all features common to both A/D’s share
common pins. The 24-pin ML6401-1 is not, however, a
direct replacement for the CXD1175. The architectural
differences between the two parts result in slightly
different application circuits only in the area of the
reference pins.
The 1175 brings the top and bottom of the reference
ladder to external pins (denoted VRT and VRB
respectively), and provides two additional pins (VRTS and
VRBS) which can be used to bias the ladder. There are
three major differences in the use of the 24-pin ML6401:
First, there is no single resistor ladder which can be
brought out to users in order to vary gain and offset.
Second, the 24-pin ML6401 cannot handle full scale
ranges of VDDA volts. And third, where the 1175
architecture has two voltages (VRT and VRB) which fix
the two endpoints of the conversion range (code 255 and
code 0), the 24-pin ML6401 has one voltage (VREF)
which affects only full scale range (code 255 – code 0),
and one voltage (V
IN
–) which affects only bias (code
128). An internally generated VREF
OUT
(1 volt) is brought
to pin 16 (VRTS of 1175), and an internally generated V
IN-
BIAS
(1.5 volts) is brought to pin 22 (VRBS of 1175). This
allows the following four modes of operation:
1.
CXD1175
— See Figure 5. Connect VRTS to VRT and
VRBS to VRB. The ladder will have 2V across it (equal
to the full scale range), which varies with supply.
ML6401
— With pin 16 connected to pin 17, and pin
22 connected to pin 23, the A/D will supply internally
generated bandgap biases, making full scale range 2V
and bias (code 128) 1.5V. This is a virtual drop in for
an 1175 with pins 16 and 17 shorted, and pins 22 and
23 shorted (0.1V bias difference).
2.
CXD1175
— See Figure 6. Leave VRTS and VRBS
open, and drive VRT and VRB with external voltages.
The 1175 spec allows VRT-VRB to equal from 1.8V to
VDD
A
volts. This allows users the flexibility to supply
higher quality references (higher precision, lower
noise), and change the full scale range of the A/D
(these voltages can be varied to effectively implement
a VGA). Also, the offset of the A/D can be varied.
ML6401
— Leave pin 16 and pin 22 open, and drive
pin 17 and pin 23 with external voltages. The full scale
range will be 2
′
pin 17 volts, and the bias (code 128)
will occur at pin 23 ±2% volts. The full scale range of
the A/D must be kept below 4V, but the part is only
specified for full scale range of 2V.
3.
CXD1175
— Connect VRBS to VRB and leave VRTS
open while driving VRT with an external voltage. This
allows similar functionality to number 2(above), but
the bias voltage (code 0) will move when the full scale
range is changed.
ML6401
— Open pin 16, drive pin 17 externally, and
connect pin 22 to pin 23. The full scale range will be
2
′
pin 17 volts, and the bias (code 128) will occur at
1.5 volts (internally generated from bandgap). The full
scale range of the A/D must be kept below 4 volts, but
the part is only specified for full scale range of 2 volts.
4.
CXD1175
— Connect VRTS to VRT and leave VRBS
open while driving VRB with an external voltage. This
allows similar functionality to #2 preceding, but the
bias voltage (code 0) will move when the full scale
range is changed.
ML6401
— Connect pin 16 to pin 17, open pin 22 and
drive pin 23 externally. The full scale range will be 2V
(internally generated from bandgap), and the bias
(code 128) will occur at pin 23 ±2% volts.
FUNCTIONAL DESCRIPTION
(Continued)
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