- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377971 > ML6401 (Fairchild Semiconductor Corporation) 8-Bit 20MSa/s Video A/D Converter(8位20MSa/s視頻A/D轉(zhuǎn)換器) PDF資料下載
參數(shù)資料
| 型號： | ML6401 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 8-Bit 20MSa/s Video A/D Converter(8位20MSa/s視頻A/D轉(zhuǎn)換器) |
| 中文描述： | 8位20MSa / s的視頻A / D轉(zhuǎn)換器（8位20MSa /秒視頻的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 233K |
| 代理商： | ML6401 |
5
ML6401
FUNCTIONAL DESCRIPTION
The Micro Linear ML6401 is a single-chip video A/D
converter IC which is intended for analog to digital
conversion of 2V
P-P
signals at rates up to 20MSa/S.
Incorporating both bias and clock generation, it forms a
complete solution for data conversion. The operating
power dissipation is typically less than 200mW. The
ML6401 is designed to offer low power dissipation and a
high level of integration resulting in an optimized
solution. The device consists of an input track and hold, a
three stage pipelined A/D converter, digital error
correction circuitry, internal dual non-overlapping clock
generator, and internal voltage reference.
INPUT TRACK AND HOLD
The input track and hold consists of a differential
capacitor feedback amplifier. The input capacitance,
including pin protection and transmission gate, is 4pF.
The input to the track and hold can be driven
differentially, or single-ended. Single-ended operation
uses an internal or external reference to bias the negative
input. The full scale range can be set externally, or
supplied from an internal source. The track and hold
samples the input signal during the positive half cycle of
the input clock, and holds the last value of V
IN
during the
negative half cycle of the input clock. The settling time of
the amplifier is less than 20ns.
A/D CONVERTER
A/D conversion is performed via a three stage pipelined
architecture. The first two stages quantize their input
signal to three bits, then subtract the result from the input
and amplify the difference by a factor of four. This creates
a residue signal which spans the full scale range of the
following converter. The subtraction and amplification is
performed via a differential capacitor feedback amplifier,
similar to the input track and hold. The third stage
quantizes the signal to four bits. One bit from each of the
last two stages is used for error correction.
The first stage A/D performs the conversion at the end of
the track and hold period, approximately one-half cycle
after the input was sampled. The second stage A/D
performs the conversion one half cycle later, after the
subtraction/amplification of the first stage has settled. The
third stage A/D performs the conversion after another
one-half cycle delay, when the second stage has settled.
Error correction is then performed, and, one clock cycle
later, data is transferred to the output latch. This permits
the data to be read 3 clocks after the sample was taken.
This technique results in lower input capacitance, lower
harmonic distortion, and higher signal to noise ratios than
the classical two step parallel technique, providing a
greater number of effective bits.
CLOCK GENERATION
The ML6401 typically requires an input clock that if
running at 20MHz would have a low time of 25ns, and a
high time of 25ns. This input is applied to a clock
generation circuit which creates the two non-overlapping
clock signals required by the feedback amplifiers.
Pipeline delay is the number of clock cycles between
conversion initiation and the associated output data being
made available. New output data is provided every clock
cycle.
Figure 2. Typical Effective Bits vs. Input Signal Frequency
8
7
6
E
FREQUENCY
1
3
5
10
8
2
4
9
6
7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ML6415 | S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation |
| ML6415CS | S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation |
| ML6416 | S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation |
| ML6416CS | S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation |
| ML6421 | Triple Phase and Sinx/x Equalized, Low-Pass Video Filter(三相和Sinx/x相均衡的視頻低通濾波器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML6401CS-1 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:8-Bit 20 MSPS A/D Converter |
| ML6401CS-3 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:8-Bit 20 MSPS A/D Converter |
| ML6411 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Programmable Video Digitizer with Selectable Gain and Clamps |
| ML64114R | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:AIGaAs LASER DIODES |
| ML64116R | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FOR OPTICAL INFORMATION SYSTEMS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。