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參數(shù)資料
| 型號： | ML6431 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Genlocking Sync Generator with Digital Audio Clock for NTSC, PAL & VGA(用于NTSC, PAL & VGA數(shù)字式音頻同步時鐘發(fā)生器) |
| 中文描述： | 同步鎖相同步發(fā)生器用于NTSC，PAL與數(shù)字音頻時鐘 |
| 文件頁數(shù)： | 18/33頁 |
| 文件大?。?/td> | 384K |
| 代理商： | ML6431 |
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ML6430/ML6431
18
REGISTER
DATA
BIT
DESCRIPTION
VALUE RANGE
BIT CODE
RANGE
0
0
PulsePol 0
C
SYNC
Polarity
High Active-Low Active
0 or 1
0
1
PulsePol 1
H/V Blank Polarity
High Active-Low Active
0 or 1
0
2
PulsePol 2
S/B Clamp Polarity
High Active-Low Active
0 or 1
0
3
Clk 4X
Select 4X Clock
Low 1X Clock = 13.5MHz
High 4X Clock = 54MHz
0 or 1
1
0
Pixel0
Pix Counter Load Bit 0
1
1
Pixel1
Pix Counter Load Bit 1
1
2
Pixel2
Pix Counter Load Bit 2
1
3
Pixel3
Pix Counter Load Bit 3
2
0
Pixel4
Pix Counter Load Bit 4
2
1
Pixel5
Pix Counter Load Bit 5
2
2
Pixel6
Pix Counter Load Bit 6
2
3
Pixel7
Pix Counter Load Bit 7
3
0
Pixel8
Pix Counter Load Bit 8
3
1
Pixel9
Pix Counter Load Bit 9
3
2
Pixel10
Pix Counter Load Bit 10
3
3
Burst
Burst Gate Enable
Low = Back Porch Clamp
High = Burst Gate
0 or 1
4
0
CSyncRaw
(or C
SYNC
Regen)
Low = regenerated C
SYNC
High = raw C
SYNC
0 or 1
4
1
RawClamp
(or Clamp Regen)
Low = regenerated Clamp
High = raw Clamp
0 or 1
4
2
TTL Sync
TTL horizontal + vertical
Sync Input
Low = sync separator active
High = TTL horiz + vert sync input
0 or 1
4
3
WideBlank
(or Narrow)
Low = narrow blanking
High = wide blanking
0 or 1
5
0
HDelay0
5
1
HDelay1
5
2
HDelay2
5
3
HDelay3
6
0
HDelay4
6
1
HDelay5
6
2
HDelay6
6
3
Noise Gating 3/4 line lockout
Low = noise gating on
High = noise gating off
0 or 1
Numerical value taken as unsigned
binary. Actual no. of pixels is:
512
100
2
+
P
:
Do not vary pixel [10:0] by more than
±6% from nominal.
1024 > no. of pixels > 512 and
f
NOM
x 1.06 > f
NEW
> f
NOM
x 0.94
nom = ~011 0000 0000
max = 011 0011 0000
min = 010 1101 0000
H Delay parameter allows
moving the entire constellation
of output pulses relative to the
incoming H
SYNC
. Exception:
Sync Tip clamp may be
selected for delay or triggered
from incoming sync
depending on application.
7-bit Horizontal Delay parameter.
Values:
–64p< Hdly < 63p, p = 1/F
4XCLK
0000000 to 1111111:
0000000 means –64p
1111111 means +63p
1000000 means 0p
Table 10. ML6430 Register Map
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