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參數(shù)資料
| 型號(hào)： | ML6431 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Genlocking Sync Generator with Digital Audio Clock for NTSC, PAL & VGA(用于NTSC, PAL & VGA數(shù)字式音頻同步時(shí)鐘發(fā)生器) |
| 中文描述： | 同步鎖相同步發(fā)生器用于NTSC，PAL與數(shù)字音頻時(shí)鐘 |
| 文件頁(yè)數(shù)： | 21/33頁(yè) |
| 文件大?。?/td> | 384K |
| 代理商： | ML6431 |
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ML6430/ML6431
21
REGISTER
DATA
BIT
DESCRIPTION
VALUE RANGE
BIT CODE
RANGE
7
0
DisAutoVCR
0=Auto VCR Detect ON
1=Disable Auto VCR Detect
0 or 1
7
1
Test 1
For test mode only:
No user programmable features. Set to 0
0
7
2
Ext 54
Clock IN
Low = Pin 3 is
SLEEP
High = Pin 3 is Ext 54MHz Clock
0 or 1
7
3
PHERROUT or AUDIOCLK
Low=Pin 16 is Audio CLK, Pin 3 is
SLEEP
High=Pin 16 is PHERROUT, Pin 3
is
RESET
0 or 1
8
0
FAud0
AudioClk Freq Bit 0
00 = 48kHz, 01 = 44.1kHz, 10 = 32kHz
00 to 10
8
1
FAud1
AudioClk Freq Bit 1
8
2
VCR
Enable VCR Mode
High = Enabled, Low = Disabled
8
3
SLEEP
Power Down Mode
High = Power Down, Low = Normal
9
0
Thresh0
Select ‘Out of Lock’ Threshold
00 = 2.5 Pixels
10 = 1.0 Pixels
00 to 11
9
1
Thresh1
01 = 2.5 Pixels
11 = 4.0 Pixels
9
2
VGA
Enable VGA Mode
High = Enabled, Low = Disabled
0 or 1
9
3
Div4
Enable /4 on M/N Loop
High = Enabled, Low = Disabled
0 or 1
10
0
FStd0
Freq Std Sel Bit 0
000 = NTSC SqPix 011 = PAL 601
000 to 100
10
1
FStd1
Freq Std Sel Bit 1
001 = PAL Sq Pix 100 = NTSC 4Fsc
10
2
FStd2
Freq Std Sel Bit 2
010 = NTSC 601
10
3
PALX
TAL
Enable PAL Ref Freq
High = Enabled, Low = Disabled
0 or 1
Table 11. ML6431 Register Map (Continued)
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