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參數(shù)資料
| 型號： | ML6431 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Genlocking Sync Generator with Digital Audio Clock for NTSC, PAL & VGA(用于NTSC, PAL & VGA數(shù)字式音頻同步時鐘發(fā)生器) |
| 中文描述： | 同步鎖相同步發(fā)生器用于NTSC，PAL與數(shù)字音頻時鐘 |
| 文件頁數(shù)： | 4/33頁 |
| 文件大?。?/td> | 384K |
| 代理商： | ML6431 |
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ML6430/ML6431
4
PIN DESCRIPTION
(Continued)
PIN
NAME
FUNCTION
23
H
RESET
Horizontal reset; active low for one
half pixel.
24
V
BLANK
Vertical blanking, active low
25
H
BLANK
Horizontal blanking, active low
26
C
SYNC
Composite sync output. May be either
the raw output of sync slicer, or
regenerated signal from internal pulse
generators. If raw slicer output is
selected, then signals disappear when
input signal disappears. If regenerated
output is selected, then signal is
always present regardless of input
conditions. Preset modes produce
regenerated sync.
27
B
CLAMP
/BURST
This is a dual mode pin. User may
select either a back porch clamp pulse
or a burst gate pulse via the serial
control bus. Preset is B
CLAMP
pulse.
PIN
NAME
FUNCTION
28
S
CLAMP
Sync clamp pulse occurs just after
leading edge of sync. Duration is
typically less than 50% of sync pulse
to avoid problems with equalizers in
the vertical interval, active high.
29
V
CC
D
Digital supply pin for digital PLL.
30
GND D
Digital ground pin for digital PLL.
31
P0
This is a three-state pin: low means
serial bus is enabled, high or
unconnected (high Z) means presets
are active. Refer to Table 7.
32
P1
This is a three state pin. Refer to
Table 7. If presets are disabled pin
is ignored.
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