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參數(shù)資料
| 型號： | ML6431 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Genlocking Sync Generator with Digital Audio Clock for NTSC, PAL & VGA(用于NTSC, PAL & VGA數(shù)字式音頻同步時鐘發(fā)生器) |
| 中文描述： | 同步鎖相同步發(fā)生器用于NTSC，PAL與數(shù)字音頻時鐘 |
| 文件頁數(shù)： | 22/33頁 |
| 文件大小： | 384K |
| 代理商： | ML6431 |
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ML6430/ML6431
22
FUNCTIONAL DESCRIPTION
(Continued)
SERIAL BUS OPERATION
The serial bus control in the ML6430/ML6431 has two
levels of addressing: Device Addressing and Register
Addressing.
Device Addressing
: Figure 5 shows the physical
waveforms generated in order to address the ML6430/
ML6431. There are six basic parts of the waveform:
1. Start Indication: Clock Cycle 0
2. Device Address Shifted: Clock Cycle 1 through 8
3. Device Address Strobed and Decoded: Clock Cycle 9
4. Data Shifted : Clock Cycle 10 through 17
5. Data Strobed into Appropriate Register: Clock Cycle 18
6. Stop indication: Clock Cycle 19
Register Addressing
: Figure 6 shows the register map of
the ML6430/6431. There are two basic parts of each
received data byte: Address Nibble and Data Nibble
1. Address Nibble: The upper 4 bits of the data byte
gives the register number in which to place the
data.
2. Data Nibble: The lower 4 bits of the data byte is
the data to be placed in the currently addressed
register nibble.
Figure 6. Definition of DATA FORMAT on Serial Data Bus
S
DATA
S
CLK
STOP
MSB
MSB
A1
A0
A6
A7
0
1
2
7
8
9
10
11
16
17
18
D7
D6
D1
D0
S
CLK
:
S
CLK
:
S
DATA
:
S
CLK
:
S
CLK
:
S
DATA
:
S
CLK
:
S
DATA
;
9th pulse strobes address decoder
Rising edge enables data transfer
Value set to A6, Device Address (MSB-1)
Falling edge disables data transfer
Rising edge enables data transfer
Value set to A7, Device Address MSB
Falling edge in prep for first address transfer
Falling edge with S
CLK
Hi means start of sequence
S
DATA
:
S
DATA
:
S
CLK
:
S
CLK
:
S
DATA
:
S
CLK
:
S
CLK
:
S
DATA
:
Rising edge with S
CLK
Hi = STOP
Value set low in prep for STOP
18th pulse strobes data shift register
Rising edge enables data transfer
Value set to D6, Data MSB-1
Falling edge disables data transfer
Rising edge enables data transfer
Value set to D7, Data MSB
Figure 5. Definition of START & STOP on Serial Data Bus
S
DATA
S
CLK
START
STOP
t
RISE
t
FALL
t
SET/START
All Other S
DATA
Transitions Must Occur While S
CLK
is Low
START: A Falling Edge on the S
DATA
While S
CLK
is Held High
STOP: A Rising Edge on the S
DATA
While S
CLK
is Held High
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