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參數(shù)資料
| 型號： | ML674000 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | CMOS 32-Bit ARM-Based General-Purpose Single-Chip Microcontroller(基于ARM的32位CMOS單片機) |
| 中文描述： | 的CMOS 32位基于ARM通用單芯片微控制器（基于ARM公司的32位的CMOS單片機） |
| 文件頁數(shù)： | 10/42頁 |
| 文件大?。?/td> | 529K |
| 代理商： | ML674000 |
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PEDL674000-02
OKI Semiconductor
ML674000
8/38
PIN DESCRIPTION
Pin
Number
Pin Name
I/O
Description
Primary/
Secondary
Logic
System
42
RESET_N
I
Reset input
—
Negative
45
OSC0
I
Crystal oscillator connection or external clock input.
Connect a crystal oscillator (16 MHz to 33 MHz), if used, to OSC0
and OSC1_N.
—
46
OSC1_N
O
Crystal oscillator connection.
Leave this pin unconnected if using external clock input.
—
10
Debugging support. See Appendix A [pending] for specific uses.
TBE
I
Test pin. Connect to ground.
—
Negative
3
DBGRQ
I
Debugging pin. Normally connect to ground.
—
Positive
4
DBGACK
O
Debugging pin. Normally leave open.
—
Positive
9
TCK
I
Debugging pin. Normally connect to ground.
—
—
8
TMS
I
Debugging pin. Normally drive at High level.
—
Positive
7
nTRST
I
Debugging pin. Normally connect to ground.
—
Negative
5
TDI
I
Debugging pin. Normally drive at High level.
—
Positive
6
General-purpose I/O ports
TDO
O
Debugging pin. Normally leave open.
—
Positive
11-18,
35-36,
91-93,
95-97
PIOA[15:0]
I/O
General-purpose port.
Not available for use as port pins when secondary functions are
in use.
Primary
Positive
109-110,
112-115,
117-118,
121-126
1-2
External Bus
PIOB[15:0]
I/O
General-purpose port.
Not available for use as port pins when secondary functions are
in use. Note that enabling DRAM controller with MODE[2:0]
inputs permanently configures PIOB[15:9] for their secondary
functions, making them unavailable for use as port pins.
Primary
Positive
91-96
XA[23:19]
O
Address bus to external RAM, external ROM, external I/O banks,
and external DRAM. After a reset, these pins are configured for
their primary function (PIOA[14:10]).
Secondary
Positive
67-75,
78-81,
84-88
XA[18:0]
O
Address bus to external RAM, external ROM, external I/O banks,
and external DRAM
—
Positive
48-55,
57-60,
62-65
XD[15:0]
I/O
Data bus to external RAM, external ROM, external I/O banks, and
external DRAM
—
Positive
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