參數(shù)資料
型號(hào)： ML674000
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： CMOS 32-Bit ARM-Based General-Purpose Single-Chip Microcontroller(基于ARM的32位CMOS單片機(jī))
中文描述： 的CMOS 32位基于ARM通用單芯片微控制器（基于ARM公司的32位的CMOS單片機(jī)）
文件頁(yè)數(shù)： 15/42頁(yè)
文件大?。?/td> 529K
代理商： ML674000
PEDL674000-02
OKI Semiconductor
ML674000
13/38
Serial Interface
This LSI contains two channels of serial interface.
(1)
Start-stop synchronous serial interface without FIFO: 1 channel
This serial interface is incorporated in μPLAT-7B.
Start-stop synchronous serial interface with 16-byte FIFO: 1 channel
This is ACE (Asynchronous Communication Element) equivalent in function to 16550A. It has 16-byte
FIFO in both sending and receiving.
(2)
PIO
This LSI contains two channels 16-bit parallel port.
(1)
(2)
(3)
(4)
Input or output can be selected for each bit.
Interrupt can be used for all 16 bits of each channel and interrupt is possible for each channel.
Interrupt mask and interrupt mode (level) can be set for all bits.
Input state immediately after reset.
AD Converter
Successive approximation type AD converter.
(1)
(2)
(3)
(4)
(5)
10 bits x 8 channels
Sample hold function
Scan mode and select mode are supported
Interrupt is generated after completion of conversion.
Conversion time: shortest about 5 μs.
DMAC
Two channels of direct memory access controller which transfers data between memory and memory, between
I/O and memory and between I/O and I/O.
(1)
(2)
Number of channels: 2 channels
Channel priority level:
Fixed mode
Channel priority level is always fixed (channel 0 > 1).
Roundrobin
Priority level of the channel requested for transfer is kept lowest.
Maximum number of transfers: 65,536 times (64K times)
Data transfer size: Byte (8 bits), half-word (16 bits), word (32 bits)
Bus request system:
Cycle steal mode
Bus request signal is asserted for each DMA transfer cycle.
Burst mode:
Bus request signal is asserted until all transfers of transfer cycles are
complete.
DMA transfer request:
Software request
By setting the software transfer request bit inside DMAC, the CPU starts DMA
transfer.
External request
DMA transfer is started by external request allocated to each channel.
Interrupt request:
Interrupt request is generated in CPU after the end of DMA transfers for the set
number of transfer cycles or after occurrence of error.
Interrupt request signal is output separately for each channel.
Interrupt request signal output can be masked for each channel.
(3)
(4)
(5)
(6)
(7)
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