![](http://datasheet.mmic.net.cn/330000/ML674000_datasheet_16440226/ML674000_8.png)
PEDL674000-02
OKI Semiconductor
ML674000
6/38
Primary Function
Secondary Function
Pin
Symbol
Type
Description
Symbol
Type
Description
80
81
82
GND_CORE
GND
83
VDD_CORE
VDD
84
XA[13]
85
XA[14]
86
XA[15]
87
XA[16]
88
XA[17]
89
GND_IO
90
XA[18]
91
PIOA[10]
92
PIOA[11]
93
PIOA[12]
94
VDD_IO
95
PIOA[13]
96
PIOA[14]
97
PIOA[15]
98
XOE_N
99
XWE_N
100
GND_IO
101
XBWE_N[0]
102
XBWE_N[1]
103
XROMCS_N
104
XRAMCS_N
105
XIOCS_N[0]
106
XIOCS_N[1]
107
GND_CORE
GND
108
VDD_CORE
VDD
109
PIOB[0]
110
PIOB[1]
111
VDD_IO
112
PIOB[2]
113
PIOB[3]
114
PIOB[4]
115
PIOB[5]
116
GND_IO
117
PIOB[6]
118
PIOB[7]
119
XBS_N[0]
120
XBS_N[1]
XA[11]
O
O
External memory access address output port
—
XA[12]
External memory access address output port
—
GND for CORE
—
Power supply for CORE
—
O
O
O
O
O
O
O
I/O
I/O
I/O
VDD
I/O
I/O
I/O
O
O
GND
O
O
O
O
O
O
External memory access address output port
—
External memory access address output port
—
External memory access address output port
—
External memory access address output port
—
External memory access address output port
—
GND for I/O
—
External memory access address output port
—
General port (with interrupt function)
XA[19]
O
O
O
External memory access address output port
General port (with interrupt function)
XA[20]
External memory access address output port
General port (with interrupt function)
XA[21]
External memory access address output port
Power supply for I/O
General port (with interrupt function)
XA[22]
O
O
O
External memory access address output port
General port (with interrupt function)
XA[23]
External memory access address output port
General port (with interrupt function)
XWR
Transfer direction of external bus
Output enable (excluding SDRAM)
—
Write enable
—
GND for I/O
Byte write enable (LSB)
—
Byte write enable (MSB)
—
External ROM chip select
—
External RAM chip select
—
IO bank 0 chip select
—
IO bank 1 chip select
—
GND for CORE
—
Power supply for CORE
—
I/O
I/O
VDD
I/O
I/O
I/O
I/O
GND
I/O
I/O
O
O
General port (with interrupt function)
DREQ0
I
DMA request signal (CH0)
General port (with interrupt function)
DREQCLR0
O
DREQ clear signal (CH0)
Power supply for I/O
—
General port (with interrupt function)
DREQ1
I
DMA request signal (CH1)
General port (with interrupt function)
DREQCLR1
O
O
O
DREQ clear signal (CH1)
General port (with interrupt function)
TCOUT0
DMAC Terminal Count (CH0)
General port (with interrupt function)
TCOUT1
DMAC Terminal Count (CH1)
GND for I/O
—
General port (with interrupt function)
PWMOUT[0]
O
O
PWM output (CH0)
General port (with interrupt function)
PWMOUT[1]
PWM output (CH1)
External bus byte select (LSB)
—
External bus byte select (MSB)
—