參數(shù)資料
型號: ML9044
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: DOT MATRIX LCD CONTROLLER DRIVER
中文描述: 點陣LCD控制器驅(qū)動
文件頁數(shù): 15/55頁
文件大?。?/td> 538K
代理商: ML9044
Semiconductor
ML9044
15/54
FUNCTIONAL DESCRIPTION
Instruction Register (IR), Data Register (DR), and Expansion Instruction Register (ER)
These registers are selected by setting the level of the Register Selection input pins RS
0
and RS
1
.
The DR is selected when both RS
0
and RS
1
are “H”. The IR is selected when RS0 is “L” and RS
1
is “H”. The ER is selected when both RS
0
and RS
1
are “L”. (When RS
0
is “H” and RS
1
is “L”, the
ML9044 is not selected.)
The IR stores an instruction code and the address code of the display data RAM (DDRAM) or the
character generator RAM (CGRAM).
The microcontroller (CPU) can write to the IR but cannot read from the IR.
The ER stores a contrast adjusting code and the address code of the arbitrator RAM (ABRAM).
The CPU can write to or read from the ER.
The DR stores data to be written in the DDRAM, ABRAM and CGRAM and also stores data read
from the DDRAM, AMRAM and CGRAM.
The data written in the DR by the CPU is automatically written in the DDRAM, ABRAM or
CGRAM.
When an address code is written in the IR or ER, the data of the specified address is automatically
transferred from the DDRAM, ABRAM or CGRAM to the DR. The data of the DDRAM, ABRAM
and CGRAM can be checked by allowing the CPU to read the data stored in the DR.
After the CPU writes data in the DR, the data of the next address in the DDRAM, ABRAM or
CGRAM is selected to be ready for the next writing by the CPU. Similarly, after the CPU reads
the data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is set in the
DR to be ready for the next reading by the CPU.
Writing in or reading from these 3 registers is controlled by changing the status of the R/
W
(Read/Write) pin.
Table 1 R/
W
pin status and register operation
Busy Flag (BF)
The status “1” of the Busy Flag (BF) indicates that the ML9044 is carrying out internal operation.
When the BF is “1”, any new instruction is ignored.
When R/
W
= “H”, RS
0
= “L” and RS
1
= “H”, the data in the BF is output to the DB
7
.
New instructions should be input when the BF is “0”.
When the BF is “1”, the output code of the address counter (ADC) is undefined.
R/
W
L
H
L
H
L
H
RS
0
L
L
H
H
L
L
RS
1
H
H
H
H
L
L
Operation
Writing in the IR
Reading the Busy flag (BF) and the address counter (ADC)
Writing in the DR
Reading from the DR
Writing in the ER
Reading the contrast code
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