參數(shù)資料
型號: ML9044
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: DOT MATRIX LCD CONTROLLER DRIVER
中文描述: 點陣LCD控制器驅動
文件頁數(shù): 38/55頁
文件大?。?/td> 538K
代理商: ML9044
Semiconductor
ML9044
38/54
Expansion Instruction Codes
The busy status of the ML9044 is rather longer than the cycle time of the CPU, since the internal
processing of the ML9044 starts at a timing which does not affect the display on the LCD. In the
busy status (Busy Flag is “1”), the ML9041 executes the Busy Flag Read instruction only.
Therefore, the CPU should ensure that the Busy Flag is “0” before sending an expansion
instruction code to the ML9044.
1) Arbitrator Display Line Set
This expansion instruction code sets the Arbitrator display line. The relationship between the
status of this bit and the common outputs is as follows:
2) Contrast Adjusting Data Write
RS
1
0
RS
0
0
R/
W
0
DB
7
0
DB
6
0
DB
5
0
DB
4
0
DB
3
0
DB
2
0
DB
1
1
DB
0
AS
Exparsion Instruction codes:
RS
1
0
RS
0
0
R/
W
0
DB
7
0
DB
6
0
DB
5
1
DB
4
F
4
DB
3
F
3
DB
2
F
2
DB
1
F
1
DB
0
F
0
Exparsion Instraction codes:
CSR
L
L
L
L
L
L
H
H
H
H
H
H
duty
1/9
1/9
1/12
1/12
1/17
1/17
1/9
1/9
1/12
1/12
1/17
1/17
AS bit
L
H
L
H
L
H
L
H
L
H
L
H
Shift direction
COM1
COM9
COM2
COM9, COM1
COM1
COM12
COM2
COM12, COM1
COM1
COM17
COM2
COM17, COM1
COM9
COM1
COM8
COM1, COM9
COM12
COM1
COM11
COM1, COM12
COM17
COM1
COM16
COM1, COM17
Arbitrator's comon pin
COM9
COM1
COM12
COM1
COM17
COM1
COM1
COM9
COM1
COM12
COM1
COM17
This instruction writes contrast adjusting data (F
4
to F
0
) to the contrast register.
After contrast adjusting data is written in the register, the potential (VLCD) output to the V
5
pin
varies according to the data written.
The VLCD becomes maximum when the content of the contrast register is “1F” (hexadecimal)
and becomes minimum when it is “00” (hexadecimal).
Note:
The execution time of this instruction is 37
m
s at an oscillation frequency (OSC) of 270
kHz.
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